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https://github.com/alexforencich/verilog-axi.git
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449 lines
15 KiB
Verilog
449 lines
15 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 FIFO (write)
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*/
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module axi_fifo_wr #
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(
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Width of ID signal
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parameter ID_WIDTH = 8,
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// Propagate awuser signal
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parameter AWUSER_ENABLE = 0,
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// Width of awuser signal
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parameter AWUSER_WIDTH = 1,
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// Propagate wuser signal
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parameter WUSER_ENABLE = 0,
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// Width of wuser signal
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parameter WUSER_WIDTH = 1,
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// Propagate buser signal
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parameter BUSER_ENABLE = 0,
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// Width of buser signal
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parameter BUSER_WIDTH = 1,
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// Write data FIFO depth (cycles)
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parameter FIFO_DEPTH = 32,
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// Hold write address until write data in FIFO, if possible
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parameter FIFO_DELAY = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [ID_WIDTH-1:0] s_axi_awid,
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input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [7:0] s_axi_awlen,
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input wire [2:0] s_axi_awsize,
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input wire [1:0] s_axi_awburst,
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input wire s_axi_awlock,
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input wire [3:0] s_axi_awcache,
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input wire [2:0] s_axi_awprot,
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input wire [3:0] s_axi_awqos,
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input wire [3:0] s_axi_awregion,
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input wire [AWUSER_WIDTH-1:0] s_axi_awuser,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [DATA_WIDTH-1:0] s_axi_wdata,
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input wire [STRB_WIDTH-1:0] s_axi_wstrb,
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input wire s_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s_axi_wuser,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [ID_WIDTH-1:0] s_axi_bid,
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output wire [1:0] s_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s_axi_buser,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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/*
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* AXI master interface
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*/
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output wire [ID_WIDTH-1:0] m_axi_awid,
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output wire [ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire [3:0] m_axi_awqos,
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output wire [3:0] m_axi_awregion,
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output wire [AWUSER_WIDTH-1:0] m_axi_awuser,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [DATA_WIDTH-1:0] m_axi_wdata,
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output wire [STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire [WUSER_WIDTH-1:0] m_axi_wuser,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire [BUSER_WIDTH-1:0] m_axi_buser,
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input wire m_axi_bvalid,
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output wire m_axi_bready
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);
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parameter STRB_OFFSET = DATA_WIDTH;
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parameter LAST_OFFSET = STRB_OFFSET + STRB_WIDTH;
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parameter WUSER_OFFSET = LAST_OFFSET + 1;
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parameter WWIDTH = WUSER_OFFSET + (WUSER_ENABLE ? WUSER_WIDTH : 0);
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parameter FIFO_ADDR_WIDTH = $clog2(FIFO_DEPTH);
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reg [FIFO_ADDR_WIDTH:0] wr_ptr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
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reg [FIFO_ADDR_WIDTH:0] wr_addr_reg = {FIFO_ADDR_WIDTH+1{1'b0}};
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reg [FIFO_ADDR_WIDTH:0] rd_ptr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
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reg [FIFO_ADDR_WIDTH:0] rd_addr_reg = {FIFO_ADDR_WIDTH+1{1'b0}};
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reg [WWIDTH-1:0] mem[(2**FIFO_ADDR_WIDTH)-1:0];
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reg [WWIDTH-1:0] mem_read_data_reg;
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reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
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wire [WWIDTH-1:0] s_axi_w;
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reg [WWIDTH-1:0] m_axi_w_reg;
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reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
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// full when first MSB different but rest same
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wire full = ((wr_ptr_reg[FIFO_ADDR_WIDTH] != rd_ptr_reg[FIFO_ADDR_WIDTH]) &&
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(wr_ptr_reg[FIFO_ADDR_WIDTH-1:0] == rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]));
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// empty when pointers match exactly
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wire empty = wr_ptr_reg == rd_ptr_reg;
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wire hold;
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// control signals
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reg write;
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reg read;
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reg store_output;
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assign s_axi_wready = !full && !hold;
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generate
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assign s_axi_w[DATA_WIDTH-1:0] = s_axi_wdata;
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assign s_axi_w[STRB_OFFSET +: STRB_WIDTH] = s_axi_wstrb;
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assign s_axi_w[LAST_OFFSET] = s_axi_wlast;
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if (WUSER_ENABLE) assign s_axi_w[WUSER_OFFSET +: WUSER_WIDTH] = s_axi_wuser;
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endgenerate
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generate
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if (FIFO_DELAY) begin
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// store AW channel value until W channel burst is stored in FIFO or FIFO is full
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_TRANSFER_IN = 2'd1,
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STATE_TRANSFER_OUT = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg hold_reg = 1'b1, hold_next;
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reg [8:0] count_reg = 9'd0, count_next;
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reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}, m_axi_awid_next;
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reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axi_awaddr_next;
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reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;
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reg [2:0] m_axi_awsize_reg = 3'd0, m_axi_awsize_next;
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reg [1:0] m_axi_awburst_reg = 2'd0, m_axi_awburst_next;
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reg m_axi_awlock_reg = 1'b0, m_axi_awlock_next;
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reg [3:0] m_axi_awcache_reg = 4'd0, m_axi_awcache_next;
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reg [2:0] m_axi_awprot_reg = 3'd0, m_axi_awprot_next;
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reg [3:0] m_axi_awqos_reg = 4'd0, m_axi_awqos_next;
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reg [3:0] m_axi_awregion_reg = 4'd0, m_axi_awregion_next;
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reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}, m_axi_awuser_next;
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reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
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assign m_axi_awid = m_axi_awid_reg;
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assign m_axi_awaddr = m_axi_awaddr_reg;
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assign m_axi_awlen = m_axi_awlen_reg;
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assign m_axi_awsize = m_axi_awsize_reg;
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assign m_axi_awburst = m_axi_awburst_reg;
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assign m_axi_awlock = m_axi_awlock_reg;
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assign m_axi_awcache = m_axi_awcache_reg;
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assign m_axi_awprot = m_axi_awprot_reg;
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assign m_axi_awqos = m_axi_awqos_reg;
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assign m_axi_awregion = m_axi_awregion_reg;
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assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
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assign m_axi_awvalid = m_axi_awvalid_reg;
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assign s_axi_awready = s_axi_awready_reg;
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assign hold = hold_reg;
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always @* begin
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state_next = STATE_IDLE;
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hold_next = hold_reg;
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count_next = count_reg;
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m_axi_awid_next = m_axi_awid_reg;
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m_axi_awaddr_next = m_axi_awaddr_reg;
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m_axi_awlen_next = m_axi_awlen_reg;
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m_axi_awsize_next = m_axi_awsize_reg;
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m_axi_awburst_next = m_axi_awburst_reg;
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m_axi_awlock_next = m_axi_awlock_reg;
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m_axi_awcache_next = m_axi_awcache_reg;
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m_axi_awprot_next = m_axi_awprot_reg;
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m_axi_awqos_next = m_axi_awqos_reg;
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m_axi_awregion_next = m_axi_awregion_reg;
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m_axi_awuser_next = m_axi_awuser_reg;
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m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_awready;
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s_axi_awready_next = s_axi_awready_reg;
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case (state_reg)
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STATE_IDLE: begin
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s_axi_awready_next = !m_axi_awvalid || m_axi_awready;
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hold_next = 1'b1;
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if (s_axi_awready && s_axi_awvalid) begin
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s_axi_awready_next = 1'b0;
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m_axi_awid_next = s_axi_awid;
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m_axi_awaddr_next = s_axi_awaddr;
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m_axi_awlen_next = s_axi_awlen;
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m_axi_awsize_next = s_axi_awsize;
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m_axi_awburst_next = s_axi_awburst;
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m_axi_awlock_next = s_axi_awlock;
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m_axi_awcache_next = s_axi_awcache;
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m_axi_awprot_next = s_axi_awprot;
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m_axi_awqos_next = s_axi_awqos;
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m_axi_awregion_next = s_axi_awregion;
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m_axi_awuser_next = s_axi_awuser;
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hold_next = 1'b0;
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count_next = 0;
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state_next = STATE_TRANSFER_IN;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_TRANSFER_IN: begin
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s_axi_awready_next = 1'b0;
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hold_next = 1'b0;
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if (s_axi_wready && s_axi_wvalid) begin
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count_next = count_reg + 1;
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if (s_axi_wlast) begin
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m_axi_awvalid_next = 1'b1;
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hold_next = 1'b1;
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state_next = STATE_IDLE;
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end else if (FIFO_ADDR_WIDTH < 8 && count_next == 2**FIFO_ADDR_WIDTH) begin
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m_axi_awvalid_next = 1'b1;
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state_next = STATE_TRANSFER_OUT;
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end else begin
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state_next = STATE_TRANSFER_IN;
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end
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end else begin
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state_next = STATE_TRANSFER_IN;
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end
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end
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STATE_TRANSFER_OUT: begin
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s_axi_awready_next = 1'b0;
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hold_next = 1'b0;
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if (s_axi_wready && s_axi_wvalid) begin
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if (s_axi_wlast) begin
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hold_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_TRANSFER_OUT;
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end
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end else begin
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state_next = STATE_TRANSFER_OUT;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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state_reg <= state_next;
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hold_reg <= hold_next;
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count_reg <= count_next;
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m_axi_awid_reg <= m_axi_awid_next;
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m_axi_awaddr_reg <= m_axi_awaddr_next;
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m_axi_awlen_reg <= m_axi_awlen_next;
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m_axi_awsize_reg <= m_axi_awsize_next;
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m_axi_awburst_reg <= m_axi_awburst_next;
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m_axi_awlock_reg <= m_axi_awlock_next;
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m_axi_awcache_reg <= m_axi_awcache_next;
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m_axi_awprot_reg <= m_axi_awprot_next;
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m_axi_awqos_reg <= m_axi_awqos_next;
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m_axi_awregion_reg <= m_axi_awregion_next;
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m_axi_awuser_reg <= m_axi_awuser_next;
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m_axi_awvalid_reg <= m_axi_awvalid_next;
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s_axi_awready_reg <= s_axi_awready_next;
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if (rst) begin
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state_reg <= STATE_IDLE;
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hold_reg <= 1'b1;
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m_axi_awvalid_reg <= 1'b0;
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s_axi_awready_reg <= 1'b0;
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end
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end
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end else begin
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// bypass AW channel
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assign m_axi_awid = s_axi_awid;
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assign m_axi_awaddr = s_axi_awaddr;
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assign m_axi_awlen = s_axi_awlen;
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assign m_axi_awsize = s_axi_awsize;
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assign m_axi_awburst = s_axi_awburst;
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assign m_axi_awlock = s_axi_awlock;
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assign m_axi_awcache = s_axi_awcache;
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assign m_axi_awprot = s_axi_awprot;
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assign m_axi_awqos = s_axi_awqos;
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assign m_axi_awregion = s_axi_awregion;
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assign m_axi_awuser = AWUSER_ENABLE ? s_axi_awuser : {AWUSER_WIDTH{1'b0}};
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assign m_axi_awvalid = s_axi_awvalid;
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assign s_axi_awready = m_axi_awready;
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assign hold = 1'b0;
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end
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endgenerate
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// bypass B channel
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assign s_axi_bid = m_axi_bid;
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assign s_axi_bresp = m_axi_bresp;
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assign s_axi_buser = BUSER_ENABLE ? m_axi_buser : {BUSER_WIDTH{1'b0}};
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assign s_axi_bvalid = m_axi_bvalid;
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assign m_axi_bready = s_axi_bready;
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assign m_axi_wvalid = m_axi_wvalid_reg;
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assign m_axi_wdata = m_axi_w_reg[DATA_WIDTH-1:0];
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assign m_axi_wstrb = m_axi_w_reg[STRB_OFFSET +: STRB_WIDTH];
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assign m_axi_wlast = m_axi_w_reg[LAST_OFFSET];
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assign m_axi_wuser = WUSER_ENABLE ? m_axi_w_reg[WUSER_OFFSET +: WUSER_WIDTH] : {WUSER_WIDTH{1'b0}};
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// Write logic
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always @* begin
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write = 1'b0;
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wr_ptr_next = wr_ptr_reg;
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if (s_axi_wvalid) begin
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// input data valid
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if (!full && !hold) begin
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// not full, perform write
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write = 1'b1;
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wr_ptr_next = wr_ptr_reg + 1;
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end
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end
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end
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always @(posedge clk) begin
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wr_ptr_reg <= wr_ptr_next;
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wr_addr_reg <= wr_ptr_next;
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if (write) begin
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mem[wr_addr_reg[FIFO_ADDR_WIDTH-1:0]] <= s_axi_w;
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end
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if (rst) begin
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wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
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end
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end
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// Read logic
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always @* begin
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read = 1'b0;
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rd_ptr_next = rd_ptr_reg;
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mem_read_data_valid_next = mem_read_data_valid_reg;
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if (store_output || !mem_read_data_valid_reg) begin
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// output data not valid OR currently being transferred
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if (!empty) begin
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// not empty, perform read
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read = 1'b1;
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mem_read_data_valid_next = 1'b1;
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rd_ptr_next = rd_ptr_reg + 1;
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end else begin
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// empty, invalidate
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mem_read_data_valid_next = 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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rd_ptr_reg <= rd_ptr_next;
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rd_addr_reg <= rd_ptr_next;
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mem_read_data_valid_reg <= mem_read_data_valid_next;
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if (read) begin
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mem_read_data_reg <= mem[rd_addr_reg[FIFO_ADDR_WIDTH-1:0]];
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end
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if (rst) begin
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rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
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mem_read_data_valid_reg <= 1'b0;
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end
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end
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// Output register
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always @* begin
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store_output = 1'b0;
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m_axi_wvalid_next = m_axi_wvalid_reg;
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if (m_axi_wready || !m_axi_wvalid) begin
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store_output = 1'b1;
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m_axi_wvalid_next = mem_read_data_valid_reg;
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end
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end
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always @(posedge clk) begin
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m_axi_wvalid_reg <= m_axi_wvalid_next;
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|
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if (store_output) begin
|
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m_axi_w_reg <= mem_read_data_reg;
|
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end
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|
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if (rst) begin
|
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m_axi_wvalid_reg <= 1'b0;
|
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end
|
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end
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endmodule
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