FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-14 06:42:55 +08:00
Code Issues Projects Releases Wiki Activity
verilog-axi/syn
History
Alex Forencich 38915fb533 Fix reset CDC in AXI VFIFO 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-03-30 00:12:13 -07:00
..
vivado
Fix reset CDC in AXI VFIFO
2023-03-30 00:12:13 -07:00