FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-14 06:42:55 +08:00
Code Issues Projects Releases Wiki Activity
verilog-axi/rtl
History
Alex Forencich 39dc8662b6 Remove duplicate code
2021-08-11 01:16:02 -07:00
..
arbiter.v
Remove string parameters
2021-06-02 17:04:53 -07:00
axi_adapter_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_adapter_wr.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_axil_adapter_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_axil_adapter_wr.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_axil_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_cdma_desc_mux.v
Add error reporting to DMA modules
2021-08-01 10:59:38 -07:00
axi_cdma.v
Add output FIFOs to DMA engines
2021-08-03 01:53:18 -07:00
axi_crossbar_addr.v
Remove duplicate code
2021-08-11 01:16:02 -07:00
axi_crossbar_rd.v
Remove string parameters
2021-06-02 17:04:53 -07:00
axi_crossbar_wr.v
Remove string parameters
2021-06-02 17:04:53 -07:00
axi_crossbar_wrap.py
Fix instance names in wrappers
2021-06-01 13:18:11 -07:00
axi_crossbar.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_dma_desc_mux.v
Add error reporting to DMA modules
2021-08-01 10:59:38 -07:00
axi_dma_rd.v
Add output FIFOs to DMA engines
2021-08-03 01:53:18 -07:00
axi_dma_wr.v
Add output FIFOs to DMA engines
2021-08-03 01:53:18 -07:00
axi_dma.v
Add error reporting to DMA modules
2021-08-01 10:59:38 -07:00
axi_dp_ram.v
Fix backpressure bug
2020-04-12 23:33:15 -07:00
axi_fifo_rd.v
Rewrite resets
2020-08-27 13:26:03 -07:00
axi_fifo_wr.v
Use wlast instead of awlen to detect end of write burst
2020-11-15 11:26:39 -08:00
axi_fifo.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_interconnect_wrap.py
Add wrapper generators
2020-12-04 15:21:14 -08:00
axi_interconnect.v
Remove string parameters
2021-06-02 17:04:53 -07:00
axi_ram_rd_if.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_ram_wr_if.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_ram_wr_rd_if.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_ram.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_register_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_register_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_register.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_adapter_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_adapter_wr.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_dp_ram.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_interconnect_wrap.py
Fix instance names in wrappers
2021-06-01 13:18:11 -07:00
axil_interconnect.v
Remove string parameters
2021-06-02 17:04:53 -07:00
axil_ram.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_register_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_register_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_register.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
priority_encoder.v
Remove string parameters
2021-06-02 17:04:53 -07:00