mirror of
https://github.com/alexforencich/verilog-axi.git
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269 lines
9.8 KiB
Verilog
269 lines
9.8 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 lite width adapter (read)
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*/
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module axil_adapter_rd #
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(
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of input (slave) interface data bus in bits
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parameter S_DATA_WIDTH = 32,
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// Width of input (slave) interface wstrb (width of data bus in words)
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parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
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// Width of output (master) interface data bus in bits
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parameter M_DATA_WIDTH = 32,
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// Width of output (master) interface wstrb (width of data bus in words)
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parameter M_STRB_WIDTH = (M_DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI lite slave interface
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*/
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input wire [ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [S_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready,
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/*
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* AXI lite master interface
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*/
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output wire [ADDR_WIDTH-1:0] m_axil_araddr,
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output wire [2:0] m_axil_arprot,
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output wire m_axil_arvalid,
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input wire m_axil_arready,
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input wire [M_DATA_WIDTH-1:0] m_axil_rdata,
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input wire [1:0] m_axil_rresp,
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input wire m_axil_rvalid,
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output wire m_axil_rready
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);
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parameter S_ADDR_BIT_OFFSET = $clog2(S_STRB_WIDTH);
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parameter M_ADDR_BIT_OFFSET = $clog2(M_STRB_WIDTH);
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parameter S_WORD_WIDTH = S_STRB_WIDTH;
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parameter M_WORD_WIDTH = M_STRB_WIDTH;
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parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
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parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
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// output bus is wider
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parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
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parameter DATA_WIDTH = EXPAND ? M_DATA_WIDTH : S_DATA_WIDTH;
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parameter STRB_WIDTH = EXPAND ? M_STRB_WIDTH : S_STRB_WIDTH;
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// required number of segments in wider bus
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parameter SEGMENT_COUNT = EXPAND ? (M_STRB_WIDTH / S_STRB_WIDTH) : (S_STRB_WIDTH / M_STRB_WIDTH);
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parameter SEGMENT_COUNT_WIDTH = SEGMENT_COUNT == 1 ? 1 : $clog2(SEGMENT_COUNT);
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// data width and keep width per segment
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parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
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parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
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// bus width assertions
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initial begin
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if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
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$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
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$finish;
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end
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if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
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$error("Error: AXI master interface data width not evenly divisble (instance %m)");
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$finish;
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end
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if (S_WORD_SIZE != M_WORD_SIZE) begin
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$error("Error: word size mismatch (instance %m)");
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$finish;
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end
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if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
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$error("Error: AXI slave interface word width must be even power of two (instance %m)");
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$finish;
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end
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if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
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$error("Error: AXI master interface word width must be even power of two (instance %m)");
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$finish;
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end
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end
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localparam [0:0]
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STATE_IDLE = 1'd0,
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STATE_DATA = 1'd1;
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reg [0:0] state_reg = STATE_IDLE, state_next;
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reg [SEGMENT_COUNT_WIDTH-1:0] current_segment_reg = 0, current_segment_next;
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reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
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reg [S_DATA_WIDTH-1:0] s_axil_rdata_reg = {S_DATA_WIDTH{1'b0}}, s_axil_rdata_next;
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reg [1:0] s_axil_rresp_reg = 2'd0, s_axil_rresp_next;
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reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_araddr_next;
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reg [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
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reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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reg m_axil_rready_reg = 1'b0, m_axil_rready_next;
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assign s_axil_arready = s_axil_arready_reg;
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assign s_axil_rdata = s_axil_rdata_reg;
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assign s_axil_rresp = s_axil_rresp_reg;
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assign s_axil_rvalid = s_axil_rvalid_reg;
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assign m_axil_araddr = m_axil_araddr_reg;
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assign m_axil_arprot = m_axil_arprot_reg;
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assign m_axil_arvalid = m_axil_arvalid_reg;
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assign m_axil_rready = m_axil_rready_reg;
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always @* begin
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state_next = STATE_IDLE;
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current_segment_next = current_segment_reg;
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s_axil_arready_next = 1'b0;
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s_axil_rdata_next = s_axil_rdata_reg;
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s_axil_rresp_next = s_axil_rresp_reg;
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s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
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m_axil_araddr_next = m_axil_araddr_reg;
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m_axil_arprot_next = m_axil_arprot_reg;
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m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_arready;
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m_axil_rready_next = 1'b0;
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if (SEGMENT_COUNT == 1 || EXPAND) begin
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// master output is same width or wider; single cycle direct transfer
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case (state_reg)
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STATE_IDLE: begin
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s_axil_arready_next = !m_axil_arvalid;
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if (s_axil_arready && s_axil_arvalid) begin
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s_axil_arready_next = 1'b0;
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m_axil_araddr_next = s_axil_araddr;
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m_axil_arprot_next = s_axil_arprot;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = !m_axil_rvalid;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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m_axil_rready_next = !s_axil_rvalid;
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if (m_axil_rready && m_axil_rvalid) begin
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m_axil_rready_next = 1'b0;
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if (M_WORD_WIDTH == S_WORD_WIDTH) begin
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s_axil_rdata_next = m_axil_rdata;
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end else begin
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s_axil_rdata_next = m_axil_rdata >> (m_axil_araddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_DATA_WIDTH);
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end
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s_axil_rresp_next = m_axil_rresp;
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s_axil_rvalid_next = 1'b1;
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s_axil_arready_next = !m_axil_arvalid;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_DATA;
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end
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end
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endcase
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end else begin
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// master output is narrower; may need several cycles
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case (state_reg)
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STATE_IDLE: begin
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s_axil_arready_next = !m_axil_arvalid;
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current_segment_next = 0;
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s_axil_rresp_next = 2'd0;
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if (s_axil_arready && s_axil_arvalid) begin
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s_axil_arready_next = 1'b0;
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m_axil_araddr_next = s_axil_araddr & ({ADDR_WIDTH{1'b1}} << S_ADDR_BIT_OFFSET);
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m_axil_arprot_next = s_axil_arprot;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = !m_axil_rvalid;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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m_axil_rready_next = !s_axil_rvalid;
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if (m_axil_rready && m_axil_rvalid) begin
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m_axil_rready_next = 1'b0;
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s_axil_rdata_next[current_segment_reg*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
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if (m_axil_rresp) begin
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s_axil_rresp_next = m_axil_rresp;
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end
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if (current_segment_reg == SEGMENT_COUNT-1) begin
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s_axil_rvalid_next = 1'b1;
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s_axil_arready_next = !m_axil_arvalid;
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state_next = STATE_IDLE;
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end else begin
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current_segment_next = current_segment_reg + 1;
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m_axil_araddr_next = m_axil_araddr_reg + SEGMENT_STRB_WIDTH;
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m_axil_arvalid_next = 1'b1;
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state_next = STATE_DATA;
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end
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end else begin
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state_next = STATE_DATA;
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end
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end
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endcase
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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m_axil_arvalid_reg <= 1'b0;
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m_axil_rready_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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s_axil_arready_reg <= s_axil_arready_next;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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m_axil_arvalid_reg <= m_axil_arvalid_next;
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m_axil_rready_reg <= m_axil_rready_next;
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end
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current_segment_reg <= current_segment_next;
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s_axil_rdata_reg <= s_axil_rdata_next;
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s_axil_rresp_reg <= s_axil_rresp_next;
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m_axil_araddr_reg <= m_axil_araddr_next;
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m_axil_arprot_reg <= m_axil_arprot_next;
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end
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endmodule
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