mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
322 lines
11 KiB
Python
Executable File
322 lines
11 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2015 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axi
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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port0_axi_awid = Signal(intbv(0)[8:])
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port0_axi_awaddr = Signal(intbv(0)[32:])
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port0_axi_awlen = Signal(intbv(0)[8:])
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port0_axi_awsize = Signal(intbv(0)[3:])
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port0_axi_awburst = Signal(intbv(0)[2:])
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port0_axi_awlock = Signal(intbv(0)[1:])
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port0_axi_awcache = Signal(intbv(0)[4:])
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port0_axi_awprot = Signal(intbv(0)[3:])
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port0_axi_awqos = Signal(intbv(0)[4:])
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port0_axi_awregion = Signal(intbv(0)[4:])
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port0_axi_awvalid = Signal(bool(False))
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port0_axi_wdata = Signal(intbv(0)[32:])
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port0_axi_wstrb = Signal(intbv(0)[4:])
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port0_axi_wlast = Signal(bool(False))
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port0_axi_wvalid = Signal(bool(False))
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port0_axi_bready = Signal(bool(False))
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port0_axi_arid = Signal(intbv(0)[8:])
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port0_axi_araddr = Signal(intbv(0)[32:])
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port0_axi_arlen = Signal(intbv(0)[8:])
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port0_axi_arsize = Signal(intbv(0)[3:])
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port0_axi_arburst = Signal(intbv(0)[2:])
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port0_axi_arlock = Signal(intbv(0)[1:])
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port0_axi_arcache = Signal(intbv(0)[4:])
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port0_axi_arprot = Signal(intbv(0)[3:])
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port0_axi_arqos = Signal(intbv(0)[4:])
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port0_axi_arregion = Signal(intbv(0)[4:])
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port0_axi_arvalid = Signal(bool(False))
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port0_axi_rready = Signal(bool(False))
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# Outputs
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port0_axi_awready = Signal(bool(False))
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port0_axi_wready = Signal(bool(False))
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port0_axi_bid = Signal(intbv(0)[8:])
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port0_axi_bresp = Signal(intbv(0)[2:])
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port0_axi_bvalid = Signal(bool(False))
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port0_axi_arready = Signal(bool(False))
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port0_axi_rid = Signal(intbv(0)[8:])
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port0_axi_rdata = Signal(intbv(0)[32:])
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port0_axi_rresp = Signal(intbv(0)[2:])
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port0_axi_rlast = Signal(bool(False))
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port0_axi_rvalid = Signal(bool(False))
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# AXI4 master
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axi_master_inst = axi.AXIMaster()
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axi_master_pause = Signal(bool(False))
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axi_master_logic = axi_master_inst.create_logic(
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clk,
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rst,
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m_axi_awid=port0_axi_awid,
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m_axi_awaddr=port0_axi_awaddr,
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m_axi_awlen=port0_axi_awlen,
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m_axi_awsize=port0_axi_awsize,
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m_axi_awburst=port0_axi_awburst,
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m_axi_awlock=port0_axi_awlock,
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m_axi_awcache=port0_axi_awcache,
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m_axi_awprot=port0_axi_awprot,
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m_axi_awqos=port0_axi_awqos,
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m_axi_awregion=port0_axi_awregion,
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m_axi_awvalid=port0_axi_awvalid,
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m_axi_awready=port0_axi_awready,
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m_axi_wdata=port0_axi_wdata,
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m_axi_wstrb=port0_axi_wstrb,
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m_axi_wlast=port0_axi_wlast,
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m_axi_wvalid=port0_axi_wvalid,
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m_axi_wready=port0_axi_wready,
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m_axi_bid=port0_axi_bid,
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m_axi_bresp=port0_axi_bresp,
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m_axi_bvalid=port0_axi_bvalid,
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m_axi_bready=port0_axi_bready,
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m_axi_arid=port0_axi_arid,
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m_axi_araddr=port0_axi_araddr,
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m_axi_arlen=port0_axi_arlen,
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m_axi_arsize=port0_axi_arsize,
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m_axi_arburst=port0_axi_arburst,
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m_axi_arlock=port0_axi_arlock,
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m_axi_arcache=port0_axi_arcache,
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m_axi_arprot=port0_axi_arprot,
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m_axi_arqos=port0_axi_arqos,
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m_axi_arregion=port0_axi_arregion,
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m_axi_arvalid=port0_axi_arvalid,
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m_axi_arready=port0_axi_arready,
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m_axi_rid=port0_axi_rid,
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m_axi_rdata=port0_axi_rdata,
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m_axi_rresp=port0_axi_rresp,
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m_axi_rlast=port0_axi_rlast,
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m_axi_rvalid=port0_axi_rvalid,
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m_axi_rready=port0_axi_rready,
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pause=axi_master_pause,
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name='master'
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)
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# AXI4 RAM model
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axi_ram_inst = axi.AXIRam(2**16)
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axi_ram_pause = Signal(bool(False))
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axi_ram_port0 = axi_ram_inst.create_port(
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clk,
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s_axi_awid=port0_axi_awid,
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s_axi_awaddr=port0_axi_awaddr,
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s_axi_awlen=port0_axi_awlen,
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s_axi_awsize=port0_axi_awsize,
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s_axi_awburst=port0_axi_awburst,
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s_axi_awlock=port0_axi_awlock,
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s_axi_awcache=port0_axi_awcache,
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s_axi_awprot=port0_axi_awprot,
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s_axi_awvalid=port0_axi_awvalid,
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s_axi_awready=port0_axi_awready,
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s_axi_wdata=port0_axi_wdata,
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s_axi_wstrb=port0_axi_wstrb,
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s_axi_wlast=port0_axi_wlast,
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s_axi_wvalid=port0_axi_wvalid,
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s_axi_wready=port0_axi_wready,
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s_axi_bid=port0_axi_bid,
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s_axi_bresp=port0_axi_bresp,
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s_axi_bvalid=port0_axi_bvalid,
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s_axi_bready=port0_axi_bready,
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s_axi_arid=port0_axi_arid,
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s_axi_araddr=port0_axi_araddr,
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s_axi_arlen=port0_axi_arlen,
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s_axi_arsize=port0_axi_arsize,
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s_axi_arburst=port0_axi_arburst,
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s_axi_arlock=port0_axi_arlock,
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s_axi_arcache=port0_axi_arcache,
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s_axi_arprot=port0_axi_arprot,
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s_axi_arvalid=port0_axi_arvalid,
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s_axi_arready=port0_axi_arready,
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s_axi_rid=port0_axi_rid,
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s_axi_rdata=port0_axi_rdata,
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s_axi_rresp=port0_axi_rresp,
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s_axi_rlast=port0_axi_rlast,
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s_axi_rvalid=port0_axi_rvalid,
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s_axi_rready=port0_axi_rready,
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pause=axi_ram_pause,
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name='port0'
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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def wait_normal():
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while not axi_master_inst.idle():
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yield clk.posedge
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def wait_pause_master():
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while not axi_master_inst.idle():
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axi_master_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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axi_master_pause.next = False
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yield clk.posedge
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def wait_pause_slave():
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while not axi_master_inst.idle():
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axi_ram_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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axi_ram_pause.next = False
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yield clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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print("test 1: baseline")
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current_test.next = 1
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data = axi_ram_inst.read_mem(0, 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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yield delay(100)
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yield clk.posedge
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print("test 2: direct write")
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current_test.next = 2
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axi_ram_inst.write_mem(0, b'test')
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data = axi_ram_inst.read_mem(0, 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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assert axi_ram_inst.read_mem(0,4) == b'test'
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yield clk.posedge
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print("test 3: write via port0")
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current_test.next = 3
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axi_master_inst.init_write(4, b'\x11\x22\x33\x44')
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yield axi_master_inst.wait()
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yield clk.posedge
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data = axi_ram_inst.read_mem(0, 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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assert axi_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
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yield delay(100)
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yield clk.posedge
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print("test 4: read via port0")
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current_test.next = 4
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axi_master_inst.init_read(4, 4)
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yield axi_master_inst.wait()
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yield clk.posedge
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data = axi_master_inst.get_read_data()
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assert data[0] == 4
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assert data[1] == b'\x11\x22\x33\x44'
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yield delay(100)
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yield clk.posedge
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print("test 5: various writes")
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current_test.next = 5
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for length in range(1,8):
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for offset in range(4,8):
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for size in (2, 1, 0):
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for wait in wait_normal, wait_pause_master, wait_pause_slave:
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axi_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
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axi_master_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length], size=size)
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yield wait()
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yield clk.posedge
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data = axi_ram_inst.read_mem(256*(16*offset+length), 32)
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for i in range(0, len(data), 16):
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print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
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assert axi_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
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assert axi_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
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assert axi_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
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yield delay(100)
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yield clk.posedge
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print("test 6: various reads")
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current_test.next = 6
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for length in range(1,8):
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for offset in range(4,8):
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for size in (2, 1, 0):
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for wait in wait_normal, wait_pause_master, wait_pause_slave:
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axi_master_inst.init_read(256*(16*offset+length)+offset, length, size=size)
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yield wait()
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yield clk.posedge
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data = axi_master_inst.get_read_data()
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assert data[0] == 256*(16*offset+length)+offset
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assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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os.chdir(os.path.dirname(os.path.abspath(__file__)))
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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