FPGA/verilog-axi
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verilog-axi/tb
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Alex Forencich 513a53e52d Add AXI DMA module and testbench
2018-12-27 14:21:06 -08:00
..
axi.py
Fix AXI memory model bug
2018-12-06 15:14:54 -08:00
axil.py
Don't crash when omitting read or write port connections
2018-08-16 12:50:14 -07:00
axis_ep.py
Add AXI stream endpoint module
2018-12-27 13:49:48 -08:00
test_axi_adapter_16_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_16_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_16.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_16.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_cdma_32_unaligned.py
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_cdma_32_unaligned.v
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_cdma_32.py
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_cdma_32.v
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_dma_32_32.py
Add AXI DMA module and testbench
2018-12-27 14:21:06 -08:00
test_axi_dma_32_32.v
Add AXI DMA module and testbench
2018-12-27 14:21:06 -08:00
test_axi_dma_rd_32_32_unaligned.py
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_rd_32_32_unaligned.v
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_rd_32_32.py
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_rd_32_32.v
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_wr_32_32_unaligned.py
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dma_wr_32_32_unaligned.v
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dma_wr_32_32.py
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dma_wr_32_32.v
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_fifo_delay.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_fifo_delay.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_fifo.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_fifo.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_interconnect_4x4.py
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axi_interconnect_4x4.v
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axi_ram.py
Add optional output pipeline register to AXI RAM module
2018-11-27 01:17:31 -08:00
test_axi_ram.v
Add optional output pipeline register to AXI RAM module
2018-11-27 01:17:31 -08:00
test_axi_register.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi.py
Properly handle read bursts in AXI model
2018-08-13 15:12:56 -07:00
test_axil_adapter_16_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_16_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_16.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_16.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_interconnect_4x4.py
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axil_interconnect_4x4.v
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axil_ram.py
Add AXI lite RAM module and testbench
2018-08-14 23:49:40 -07:00
test_axil_ram.v
Add AXI lite RAM module and testbench
2018-08-14 23:49:40 -07:00
test_axil_register.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil.py
Add MyHDL AXI4 Lite master model, RAM model, and testbench
2018-08-14 23:49:11 -07:00