mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
304 lines
9.2 KiB
Python
Executable File
304 lines
9.2 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axi
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module = 'axi_ram'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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DATA_WIDTH = 32
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ADDR_WIDTH = 16
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STRB_WIDTH = (DATA_WIDTH/8)
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ID_WIDTH = 8
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PIPELINE_OUTPUT = 0
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axi_awid = Signal(intbv(0)[ID_WIDTH:])
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s_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
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s_axi_awlen = Signal(intbv(0)[8:])
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s_axi_awsize = Signal(intbv(0)[3:])
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s_axi_awburst = Signal(intbv(0)[2:])
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s_axi_awlock = Signal(bool(0))
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s_axi_awcache = Signal(intbv(0)[4:])
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s_axi_awprot = Signal(intbv(0)[3:])
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s_axi_awvalid = Signal(bool(0))
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s_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
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s_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
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s_axi_wlast = Signal(bool(0))
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s_axi_wvalid = Signal(bool(0))
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s_axi_bready = Signal(bool(0))
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s_axi_arid = Signal(intbv(0)[ID_WIDTH:])
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s_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
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s_axi_arlen = Signal(intbv(0)[8:])
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s_axi_arsize = Signal(intbv(0)[3:])
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s_axi_arburst = Signal(intbv(0)[2:])
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s_axi_arlock = Signal(bool(0))
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s_axi_arcache = Signal(intbv(0)[4:])
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s_axi_arprot = Signal(intbv(0)[3:])
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s_axi_arvalid = Signal(bool(0))
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s_axi_rready = Signal(bool(0))
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# Outputs
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s_axi_awready = Signal(bool(0))
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s_axi_wready = Signal(bool(0))
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s_axi_bid = Signal(intbv(0)[ID_WIDTH:])
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s_axi_bresp = Signal(intbv(0)[2:])
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s_axi_bvalid = Signal(bool(0))
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s_axi_arready = Signal(bool(0))
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s_axi_rid = Signal(intbv(0)[ID_WIDTH:])
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s_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
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s_axi_rresp = Signal(intbv(0)[2:])
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s_axi_rlast = Signal(bool(0))
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s_axi_rvalid = Signal(bool(0))
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# AXI4 master
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axi_master_inst = axi.AXIMaster()
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axi_master_pause = Signal(bool(False))
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axi_master_logic = axi_master_inst.create_logic(
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clk,
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rst,
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m_axi_awid=s_axi_awid,
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m_axi_awaddr=s_axi_awaddr,
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m_axi_awlen=s_axi_awlen,
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m_axi_awsize=s_axi_awsize,
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m_axi_awburst=s_axi_awburst,
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m_axi_awlock=s_axi_awlock,
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m_axi_awcache=s_axi_awcache,
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m_axi_awprot=s_axi_awprot,
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m_axi_awvalid=s_axi_awvalid,
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m_axi_awready=s_axi_awready,
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m_axi_wdata=s_axi_wdata,
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m_axi_wstrb=s_axi_wstrb,
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m_axi_wlast=s_axi_wlast,
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m_axi_wvalid=s_axi_wvalid,
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m_axi_wready=s_axi_wready,
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m_axi_bid=s_axi_bid,
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m_axi_bresp=s_axi_bresp,
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m_axi_bvalid=s_axi_bvalid,
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m_axi_bready=s_axi_bready,
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m_axi_arid=s_axi_arid,
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m_axi_araddr=s_axi_araddr,
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m_axi_arlen=s_axi_arlen,
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m_axi_arsize=s_axi_arsize,
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m_axi_arburst=s_axi_arburst,
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m_axi_arlock=s_axi_arlock,
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m_axi_arcache=s_axi_arcache,
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m_axi_arprot=s_axi_arprot,
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m_axi_arvalid=s_axi_arvalid,
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m_axi_arready=s_axi_arready,
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m_axi_rid=s_axi_rid,
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m_axi_rdata=s_axi_rdata,
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m_axi_rresp=s_axi_rresp,
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m_axi_rlast=s_axi_rlast,
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m_axi_rvalid=s_axi_rvalid,
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m_axi_rready=s_axi_rready,
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pause=axi_master_pause,
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name='master'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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s_axi_awid=s_axi_awid,
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s_axi_awaddr=s_axi_awaddr,
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s_axi_awlen=s_axi_awlen,
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s_axi_awsize=s_axi_awsize,
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s_axi_awburst=s_axi_awburst,
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s_axi_awlock=s_axi_awlock,
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s_axi_awcache=s_axi_awcache,
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s_axi_awprot=s_axi_awprot,
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s_axi_awvalid=s_axi_awvalid,
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s_axi_awready=s_axi_awready,
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s_axi_wdata=s_axi_wdata,
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s_axi_wstrb=s_axi_wstrb,
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s_axi_wlast=s_axi_wlast,
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s_axi_wvalid=s_axi_wvalid,
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s_axi_wready=s_axi_wready,
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s_axi_bid=s_axi_bid,
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s_axi_bresp=s_axi_bresp,
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s_axi_bvalid=s_axi_bvalid,
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s_axi_bready=s_axi_bready,
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s_axi_arid=s_axi_arid,
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s_axi_araddr=s_axi_araddr,
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s_axi_arlen=s_axi_arlen,
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s_axi_arsize=s_axi_arsize,
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s_axi_arburst=s_axi_arburst,
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s_axi_arlock=s_axi_arlock,
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s_axi_arcache=s_axi_arcache,
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s_axi_arprot=s_axi_arprot,
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s_axi_arvalid=s_axi_arvalid,
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s_axi_arready=s_axi_arready,
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s_axi_rid=s_axi_rid,
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s_axi_rdata=s_axi_rdata,
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s_axi_rresp=s_axi_rresp,
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s_axi_rlast=s_axi_rlast,
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s_axi_rvalid=s_axi_rvalid,
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s_axi_rready=s_axi_rready
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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def wait_normal():
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while not axi_master_inst.idle():
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yield clk.posedge
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def wait_pause_master():
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while not axi_master_inst.idle():
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axi_master_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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axi_master_pause.next = False
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yield clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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yield clk.posedge
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print("test 1: read and write")
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current_test.next = 1
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addr = 4
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test_data = b'\x11\x22\x33\x44'
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axi_master_inst.init_write(addr, test_data)
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yield axi_master_inst.wait()
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yield clk.posedge
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axi_master_inst.init_read(addr, len(test_data))
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yield axi_master_inst.wait()
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yield clk.posedge
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data = axi_master_inst.get_read_data()
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assert data[0] == addr
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assert data[1] == test_data
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yield delay(100)
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yield clk.posedge
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print("test 2: various reads and writes")
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current_test.next = 2
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for length in list(range(1,8))+[1024]:
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for offset in list(range(4,8))+[4096-4]:
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for size in (2, 1, 0):
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for wait in wait_normal, wait_pause_master:
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print("length %d, offset %d, size %d"% (length, offset, size))
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#addr = 256*(16*offset+length)+offset
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addr = offset
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test_data = bytearray([x%256 for x in range(length)])
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axi_master_inst.init_write(addr-4, b'\xAA'*(length+8))
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yield axi_master_inst.wait()
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axi_master_inst.init_write(addr, test_data, size=size)
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yield wait()
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axi_master_inst.init_read(addr-1, length+2)
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yield axi_master_inst.wait()
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data = axi_master_inst.get_read_data()
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assert data[0] == addr-1
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assert data[1] == b'\xAA'+test_data+b'\xAA'
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for length in list(range(1,8))+[1024]:
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for offset in list(range(4,8))+[4096-4]:
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for size in (2, 1, 0):
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for wait in wait_normal, wait_pause_master:
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print("length %d, offset %d, size %d"% (length, offset, size))
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#addr = 256*(16*offset+length)+offset
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addr = offset
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test_data = bytearray([x%256 for x in range(length)])
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axi_master_inst.init_write(addr, test_data)
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yield axi_master_inst.wait()
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axi_master_inst.init_read(addr, length, size=size)
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yield wait()
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yield clk.posedge
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data = axi_master_inst.get_read_data()
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assert data[0] == addr
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assert data[1] == test_data
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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