mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-28 07:02:56 +08:00
721 lines
27 KiB
Verilog
721 lines
27 KiB
Verilog
/*
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 virtual FIFO (decoder)
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*/
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module axi_vfifo_dec #
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(
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// Width of input segment
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parameter SEG_WIDTH = 32,
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// Segment count
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parameter SEG_CNT = 2,
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = SEG_WIDTH*SEG_CNT/2,
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// Use AXI stream tkeep signal
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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// Use AXI stream tlast signal
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parameter AXIS_LAST_ENABLE = 1,
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// Propagate AXI stream tid signal
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parameter AXIS_ID_ENABLE = 0,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// Propagate AXI stream tdest signal
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parameter AXIS_DEST_ENABLE = 0,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// Propagate AXI stream tuser signal
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parameter AXIS_USER_ENABLE = 1,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Segmented data input (from virtual FIFO channel)
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*/
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input wire fifo_rst_in,
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input wire [SEG_CNT*SEG_WIDTH-1:0] input_data,
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input wire [SEG_CNT-1:0] input_valid,
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output wire [SEG_CNT-1:0] input_ready,
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input wire [SEG_CNT*SEG_WIDTH-1:0] input_ctrl_data,
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input wire [SEG_CNT-1:0] input_ctrl_valid,
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output wire [SEG_CNT-1:0] input_ctrl_ready,
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/*
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* AXI stream data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
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/*
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* Status
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*/
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output wire sts_hdr_parity_err
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);
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parameter AXIS_KEEP_WIDTH_INT = AXIS_KEEP_ENABLE ? AXIS_KEEP_WIDTH : 1;
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parameter AXIS_BYTE_LANES = AXIS_KEEP_WIDTH_INT;
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parameter AXIS_BYTE_SIZE = AXIS_DATA_WIDTH/AXIS_BYTE_LANES;
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parameter AXIS_BYTE_IDX_WIDTH = $clog2(AXIS_BYTE_LANES);
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parameter BYTE_SIZE = AXIS_BYTE_SIZE;
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parameter SEG_BYTE_LANES = SEG_WIDTH / BYTE_SIZE;
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parameter EXPAND_INPUT = SEG_CNT < 2;
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parameter SEG_CNT_INT = EXPAND_INPUT ? SEG_CNT*2 : SEG_CNT;
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parameter SEG_IDX_WIDTH = $clog2(SEG_CNT_INT);
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parameter SEG_BYTE_IDX_WIDTH = $clog2(SEG_BYTE_LANES);
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parameter AXIS_SEG_CNT = (AXIS_DATA_WIDTH + SEG_WIDTH-1) / SEG_WIDTH;
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parameter AXIS_SEG_IDX_WIDTH = AXIS_SEG_CNT > 1 ? $clog2(AXIS_SEG_CNT) : 1;
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parameter AXIS_LEN_MASK = AXIS_BYTE_LANES-1;
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parameter OUT_OFFS_WIDTH = AXIS_SEG_IDX_WIDTH;
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parameter META_ID_OFFSET = 0;
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parameter META_DEST_OFFSET = META_ID_OFFSET + (AXIS_ID_ENABLE ? AXIS_ID_WIDTH : 0);
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parameter META_USER_OFFSET = META_DEST_OFFSET + (AXIS_DEST_ENABLE ? AXIS_DEST_WIDTH : 0);
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parameter META_WIDTH = META_USER_OFFSET + (AXIS_USER_ENABLE ? AXIS_USER_WIDTH : 0);
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parameter HDR_SIZE = (16 + META_WIDTH + BYTE_SIZE-1) / BYTE_SIZE;
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parameter HDR_WIDTH = HDR_SIZE * BYTE_SIZE;
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parameter HDR_LEN_WIDTH = 12;
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parameter HDR_SEG_LEN_WIDTH = HDR_LEN_WIDTH-SEG_BYTE_IDX_WIDTH;
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parameter CTRL_FIFO_ADDR_WIDTH = 5;
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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parameter CTRL_FIFO_PTR_WIDTH = CTRL_FIFO_ADDR_WIDTH + SEG_IDX_WIDTH;
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// validate parameters
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initial begin
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if (AXIS_BYTE_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
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$error("Error: AXI stream data width not evenly divisible (instance %m)");
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$finish;
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end
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if (AXIS_SEG_CNT * SEG_WIDTH != AXIS_DATA_WIDTH) begin
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$error("Error: AXI stream data width not evenly divisible into segments (instance %m)");
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$finish;
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end
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if (SEG_WIDTH < HDR_WIDTH) begin
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$error("Error: Segment smaller than header (instance %m)");
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$finish;
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end
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end
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reg frame_reg = 1'b0, frame_next, frame_cyc;
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reg last_reg = 1'b0, last_next, last_cyc;
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reg extra_cycle_reg = 1'b0, extra_cycle_next, extra_cycle_cyc;
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reg last_straddle_reg = 1'b0, last_straddle_next, last_straddle_cyc;
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reg [HDR_SEG_LEN_WIDTH-1:0] seg_cnt_reg = 0, seg_cnt_next, seg_cnt_cyc;
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reg hdr_parity_err_reg = 1'b0, hdr_parity_err_next, hdr_parity_err_cyc;
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reg out_frame_reg = 1'b0, out_frame_next, out_frame_cyc;
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reg [SEG_IDX_WIDTH-1:0] out_seg_offset_reg = 0, out_seg_offset_next, out_seg_offset_cyc;
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reg [OUT_OFFS_WIDTH-1:0] output_offset_reg = 0, output_offset_next, output_offset_cyc;
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reg [SEG_CNT_INT-1:0] out_seg_consumed;
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reg [SEG_CNT_INT-1:0] out_seg_consumed_reg = 0, out_seg_consumed_next;
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reg out_valid, out_valid_straddle, out_frame, out_last, out_abort, out_done;
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reg [SEG_CNT_INT-1:0] seg_valid;
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reg [SEG_CNT_INT-1:0] seg_valid_straddle;
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reg [SEG_CNT_INT-1:0] seg_hdr_start_pkt;
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reg [SEG_CNT_INT-1:0] seg_hdr_last;
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reg [SEG_CNT_INT-1:0] seg_hdr_last_straddle;
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reg [SEG_CNT_INT-1:0] seg_hdr_parity_err;
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reg [HDR_LEN_WIDTH-1:0] seg_hdr_len[SEG_CNT_INT-1:0];
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reg [HDR_SEG_LEN_WIDTH-1:0] seg_hdr_seg_cnt[SEG_CNT_INT-1:0];
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reg [SEG_CNT_INT-1:0] shift_out_seg_valid;
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reg [SEG_CNT_INT-1:0] shift_out_seg_valid_straddle;
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reg [SEG_CNT_INT-1:0] shift_out_seg_sop;
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reg [SEG_CNT_INT-1:0] shift_out_seg_eop;
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reg [SEG_CNT_INT-1:0] shift_out_seg_end;
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reg [SEG_CNT_INT-1:0] shift_out_seg_last;
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reg [SEG_CNT-1:0] input_ready_cmb;
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reg [SEG_CNT-1:0] input_ctrl_ready_cmb;
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reg [SEG_CNT*SEG_WIDTH-1:0] input_data_int_reg = 0, input_data_int_next;
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reg [SEG_CNT-1:0] input_valid_int_reg = 0, input_valid_int_next;
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wire [SEG_CNT_INT*SEG_WIDTH*2-1:0] input_data_full = EXPAND_INPUT ? {2{{input_data, input_data_int_reg}}} : {2{input_data}};
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wire [SEG_CNT_INT-1:0] input_valid_full = EXPAND_INPUT ? {input_valid, input_valid_int_reg} : input_valid;
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reg out_ctrl_en_reg = 0, out_ctrl_en_next;
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reg out_ctrl_hdr_reg = 0, out_ctrl_hdr_next;
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reg out_ctrl_last_reg = 0, out_ctrl_last_next;
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reg [AXIS_BYTE_IDX_WIDTH-1:0] out_ctrl_last_len_reg = 0, out_ctrl_last_len_next;
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reg [SEG_IDX_WIDTH-1:0] out_ctrl_seg_offset_reg = 0, out_ctrl_seg_offset_next;
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reg [AXIS_ID_WIDTH-1:0] axis_tid_reg = 0, axis_tid_next;
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reg [AXIS_DEST_WIDTH-1:0] axis_tdest_reg = 0, axis_tdest_next;
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reg [AXIS_USER_WIDTH-1:0] axis_tuser_reg = 0, axis_tuser_next;
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// internal datapath
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reg [AXIS_DATA_WIDTH-1:0] m_axis_tdata_int;
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reg [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep_int;
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reg m_axis_tvalid_int;
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wire m_axis_tready_int;
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reg m_axis_tlast_int;
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reg [AXIS_ID_WIDTH-1:0] m_axis_tid_int;
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reg [AXIS_DEST_WIDTH-1:0] m_axis_tdest_int;
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reg [AXIS_USER_WIDTH-1:0] m_axis_tuser_int;
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assign input_ready = input_ready_cmb;
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assign input_ctrl_ready = input_ctrl_ready_cmb;
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assign sts_hdr_parity_err = hdr_parity_err_reg;
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// segmented control FIFO
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reg [CTRL_FIFO_PTR_WIDTH+1-1:0] ctrl_fifo_wr_ptr_reg = 0, ctrl_fifo_wr_ptr_next;
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reg [CTRL_FIFO_PTR_WIDTH+1-1:0] ctrl_fifo_rd_ptr_reg = 0, ctrl_fifo_rd_ptr_next;
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reg [SEG_CNT-1:0] ctrl_mem_rd_data_valid_reg = 0, ctrl_mem_rd_data_valid_next;
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reg [SEG_CNT-1:0] ctrl_fifo_wr_sop;
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reg [SEG_CNT-1:0] ctrl_fifo_wr_eop;
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reg [SEG_CNT-1:0] ctrl_fifo_wr_end;
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reg [SEG_CNT-1:0] ctrl_fifo_wr_last;
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reg [SEG_CNT*AXIS_BYTE_IDX_WIDTH-1:0] ctrl_fifo_wr_last_len;
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reg [SEG_CNT-1:0] ctrl_fifo_wr_en;
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wire [SEG_CNT-1:0] ctrl_fifo_rd_sop;
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wire [SEG_CNT-1:0] ctrl_fifo_rd_eop;
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wire [SEG_CNT-1:0] ctrl_fifo_rd_end;
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wire [SEG_CNT-1:0] ctrl_fifo_rd_last;
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wire [SEG_CNT*AXIS_BYTE_IDX_WIDTH-1:0] ctrl_fifo_rd_last_len;
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wire [SEG_CNT-1:0] ctrl_fifo_rd_valid;
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reg [SEG_CNT-1:0] ctrl_fifo_rd_en;
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wire [SEG_CNT-1:0] ctrl_fifo_seg_full;
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wire [SEG_CNT-1:0] ctrl_fifo_seg_half_full;
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wire [SEG_CNT-1:0] ctrl_fifo_seg_empty;
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wire ctrl_fifo_full = |ctrl_fifo_seg_full;
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wire ctrl_fifo_half_full = |ctrl_fifo_seg_half_full;
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wire ctrl_fifo_empty = |ctrl_fifo_seg_empty;
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generate
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genvar n;
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for (n = 0; n < SEG_CNT; n = n + 1) begin : ctrl_fifo_seg
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reg [CTRL_FIFO_ADDR_WIDTH+1-1:0] seg_wr_ptr_reg = 0;
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reg [CTRL_FIFO_ADDR_WIDTH+1-1:0] seg_rd_ptr_reg = 0;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg seg_mem_sop[2**CTRL_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg seg_mem_eop[2**CTRL_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg seg_mem_end[2**CTRL_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg seg_mem_last[2**CTRL_FIFO_ADDR_WIDTH-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [AXIS_BYTE_IDX_WIDTH-1:0] seg_mem_last_len[2**CTRL_FIFO_ADDR_WIDTH-1:0];
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reg seg_rd_sop_reg = 0;
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reg seg_rd_eop_reg = 0;
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reg seg_rd_end_reg = 0;
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reg seg_rd_last_reg = 0;
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reg [AXIS_BYTE_IDX_WIDTH-1:0] seg_rd_last_len_reg = 0;
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reg seg_rd_valid_reg = 0;
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reg seg_half_full_reg = 1'b0;
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assign ctrl_fifo_rd_sop[n] = seg_rd_sop_reg;
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assign ctrl_fifo_rd_eop[n] = seg_rd_eop_reg;
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assign ctrl_fifo_rd_end[n] = seg_rd_end_reg;
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assign ctrl_fifo_rd_last[n] = seg_rd_last_reg;
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assign ctrl_fifo_rd_last_len[AXIS_BYTE_IDX_WIDTH*n +: AXIS_BYTE_IDX_WIDTH] = seg_rd_last_len_reg;
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assign ctrl_fifo_rd_valid[n] = seg_rd_valid_reg;
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wire seg_full = seg_wr_ptr_reg == (seg_rd_ptr_reg ^ {1'b1, {CTRL_FIFO_ADDR_WIDTH{1'b0}}});
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wire seg_empty = seg_wr_ptr_reg == seg_rd_ptr_reg;
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assign ctrl_fifo_seg_full[n] = seg_full;
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assign ctrl_fifo_seg_half_full[n] = seg_half_full_reg;
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assign ctrl_fifo_seg_empty[n] = seg_empty;
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always @(posedge clk) begin
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seg_rd_valid_reg <= seg_rd_valid_reg && !ctrl_fifo_rd_en[n];
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seg_half_full_reg <= $unsigned(seg_wr_ptr_reg - seg_rd_ptr_reg) >= 2**(CTRL_FIFO_ADDR_WIDTH-1);
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if (ctrl_fifo_wr_en[n]) begin
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seg_mem_sop[seg_wr_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]] <= ctrl_fifo_wr_sop[n];
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seg_mem_eop[seg_wr_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]] <= ctrl_fifo_wr_eop[n];
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seg_mem_end[seg_wr_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]] <= ctrl_fifo_wr_end[n];
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seg_mem_last[seg_wr_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]] <= ctrl_fifo_wr_last[n];
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seg_mem_last_len[seg_wr_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]] <= ctrl_fifo_wr_last_len[AXIS_BYTE_IDX_WIDTH*n +: AXIS_BYTE_IDX_WIDTH];
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seg_wr_ptr_reg <= seg_wr_ptr_reg + 1;
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end
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if (!seg_empty && (!seg_rd_valid_reg || ctrl_fifo_rd_en[n])) begin
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seg_rd_sop_reg <= seg_mem_sop[seg_rd_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]];
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seg_rd_eop_reg <= seg_mem_eop[seg_rd_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]];
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seg_rd_end_reg <= seg_mem_end[seg_rd_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]];
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seg_rd_last_reg <= seg_mem_last[seg_rd_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]];
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seg_rd_last_len_reg <= seg_mem_last_len[seg_rd_ptr_reg[CTRL_FIFO_ADDR_WIDTH-1:0]];
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seg_rd_valid_reg <= 1'b1;
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seg_rd_ptr_reg <= seg_rd_ptr_reg + 1;
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end
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if (rst || fifo_rst_in) begin
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seg_wr_ptr_reg <= 0;
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seg_rd_ptr_reg <= 0;
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seg_rd_valid_reg <= 1'b0;
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end
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end
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end
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endgenerate
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// parse segment headers
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integer seg;
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always @* begin
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input_ctrl_ready_cmb = 0;
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frame_next = frame_reg;
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frame_cyc = frame_reg;
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last_next = last_reg;
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last_cyc = last_reg;
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extra_cycle_next = extra_cycle_reg;
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extra_cycle_cyc = extra_cycle_reg;
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last_straddle_next = last_straddle_reg;
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last_straddle_cyc = last_straddle_reg;
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seg_cnt_next = seg_cnt_reg;
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seg_cnt_cyc = seg_cnt_reg;
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hdr_parity_err_next = 1'b0;
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hdr_parity_err_cyc = 1'b0;
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ctrl_fifo_wr_sop = 0;
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ctrl_fifo_wr_eop = 0;
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ctrl_fifo_wr_end = 0;
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ctrl_fifo_wr_last = 0;
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ctrl_fifo_wr_last_len = 0;
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ctrl_fifo_wr_en = 0;
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// decode segment headers
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for (seg = 0; seg < SEG_CNT; seg = seg + 1) begin
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seg_valid[seg] = input_ctrl_valid[seg];
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seg_hdr_start_pkt[seg] = input_ctrl_data[SEG_WIDTH*seg + 0 +: 1];
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seg_hdr_last[seg] = input_ctrl_data[SEG_WIDTH*seg + 1 +: 1];
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seg_hdr_len[seg] = input_ctrl_data[SEG_WIDTH*seg + 4 +: 12];
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seg_hdr_seg_cnt[seg] = (seg_hdr_len[seg] + SEG_BYTE_LANES) >> SEG_BYTE_IDX_WIDTH;
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seg_hdr_last_straddle[seg] = ((seg_hdr_len[seg] & (SEG_BYTE_LANES-1)) + HDR_SIZE) >> SEG_BYTE_IDX_WIDTH != 0;
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seg_hdr_parity_err[seg] = ^input_ctrl_data[SEG_WIDTH*seg + 0 +: 3] || ^input_ctrl_data[SEG_WIDTH*seg + 3 +: 13];
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end
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seg_valid_straddle = {2{seg_valid}} >> 1;
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for (seg = 0; seg < SEG_CNT; seg = seg + 1) begin
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if (!frame_cyc) begin
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if (seg_valid[seg]) begin
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if (seg_hdr_start_pkt[seg]) begin
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// start of frame
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last_cyc = seg_hdr_last[seg];
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extra_cycle_cyc = 1'b0;
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last_straddle_cyc = seg_hdr_last_straddle[seg];
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seg_cnt_cyc = seg_hdr_seg_cnt[seg];
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ctrl_fifo_wr_sop[seg] = 1'b1;
|
|
ctrl_fifo_wr_last_len[AXIS_BYTE_IDX_WIDTH*seg +: AXIS_BYTE_IDX_WIDTH] = seg_hdr_len[seg];
|
|
|
|
frame_cyc = 1'b1;
|
|
end else begin
|
|
// consume null segment
|
|
end
|
|
|
|
if (seg_hdr_parity_err[seg]) begin
|
|
hdr_parity_err_cyc = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
if (frame_cyc) begin
|
|
if (extra_cycle_cyc) begin
|
|
// extra cycle
|
|
frame_cyc = 0;
|
|
extra_cycle_cyc = 0;
|
|
|
|
ctrl_fifo_wr_eop[seg] = 1'b1;
|
|
end else if (seg_cnt_cyc == 1) begin
|
|
// last output cycle
|
|
if (last_cyc) begin
|
|
ctrl_fifo_wr_last[seg] = 1'b1;
|
|
end
|
|
|
|
if (last_straddle_cyc) begin
|
|
// last output cycle, with segment straddle
|
|
extra_cycle_cyc = 1'b1;
|
|
|
|
ctrl_fifo_wr_end[seg] = 1'b1;
|
|
end else begin
|
|
// last output cycle, no segment straddle
|
|
frame_cyc = 0;
|
|
|
|
ctrl_fifo_wr_eop[seg] = 1'b1;
|
|
ctrl_fifo_wr_end[seg] = 1'b1;
|
|
end
|
|
end else begin
|
|
// middle cycle
|
|
end
|
|
end
|
|
|
|
seg_cnt_cyc = seg_cnt_cyc - 1;
|
|
end
|
|
|
|
if (&seg_valid && !ctrl_fifo_half_full) begin
|
|
input_ctrl_ready_cmb = {SEG_CNT{1'b1}};
|
|
|
|
ctrl_fifo_wr_en = {SEG_CNT{1'b1}};
|
|
|
|
frame_next = frame_cyc;
|
|
last_next = last_cyc;
|
|
extra_cycle_next = extra_cycle_cyc;
|
|
last_straddle_next = last_straddle_cyc;
|
|
seg_cnt_next = seg_cnt_cyc;
|
|
hdr_parity_err_next = hdr_parity_err_cyc;
|
|
end
|
|
end
|
|
|
|
// re-pack data
|
|
integer out_seg;
|
|
reg [SEG_IDX_WIDTH-1:0] out_cur_seg;
|
|
|
|
always @* begin
|
|
input_ready_cmb = 0;
|
|
|
|
out_frame_next = out_frame_reg;
|
|
out_frame_cyc = out_frame_reg;
|
|
out_seg_offset_next = out_seg_offset_reg;
|
|
out_seg_offset_cyc = out_seg_offset_reg;
|
|
output_offset_next = output_offset_reg;
|
|
// output_offset_cyc = output_offset_reg;
|
|
output_offset_cyc = 0;
|
|
out_seg_consumed_next = 0;
|
|
|
|
|
|
out_ctrl_en_next = 0;
|
|
out_ctrl_hdr_next = 0;
|
|
out_ctrl_last_next = 0;
|
|
out_ctrl_last_len_next = out_ctrl_last_len_reg;
|
|
out_ctrl_seg_offset_next = out_ctrl_seg_offset_reg;
|
|
|
|
axis_tid_next = axis_tid_reg;
|
|
axis_tdest_next = axis_tdest_reg;
|
|
axis_tuser_next = axis_tuser_reg;
|
|
|
|
input_data_int_next = input_data_int_reg;
|
|
input_valid_int_next = input_valid_int_reg;
|
|
|
|
ctrl_fifo_rd_en = 0;
|
|
|
|
// apply segment offset
|
|
shift_out_seg_valid = {2{ctrl_fifo_rd_valid}} >> out_seg_offset_reg;
|
|
shift_out_seg_valid_straddle = {2{ctrl_fifo_rd_valid}} >> (out_seg_offset_reg+1);
|
|
shift_out_seg_valid_straddle[SEG_CNT-1] = 1'b0; // wrapped, so cannot be consumed
|
|
shift_out_seg_sop = {2{ctrl_fifo_rd_sop}} >> out_seg_offset_reg;
|
|
shift_out_seg_eop = {2{ctrl_fifo_rd_eop}} >> out_seg_offset_reg;
|
|
shift_out_seg_end = {2{ctrl_fifo_rd_end}} >> out_seg_offset_reg;
|
|
shift_out_seg_last = {2{ctrl_fifo_rd_last}} >> out_seg_offset_reg;
|
|
|
|
// extract data
|
|
out_valid = 0;
|
|
out_valid_straddle = 0;
|
|
out_frame = out_frame_cyc;
|
|
out_abort = 0;
|
|
out_done = 0;
|
|
out_seg_consumed = 0;
|
|
|
|
out_ctrl_seg_offset_next = out_seg_offset_reg;
|
|
|
|
out_cur_seg = out_seg_offset_reg;
|
|
for (out_seg = 0; out_seg < SEG_CNT; out_seg = out_seg + 1) begin
|
|
out_seg_offset_cyc = out_seg_offset_cyc + 1;
|
|
|
|
// check for contiguous valid segments
|
|
out_valid = (~shift_out_seg_valid & ({SEG_CNT{1'b1}} >> (SEG_CNT-1 - out_seg))) == 0;
|
|
out_valid_straddle = shift_out_seg_valid_straddle[0];
|
|
|
|
if (!out_frame_cyc) begin
|
|
if (out_valid) begin
|
|
if (shift_out_seg_sop[0]) begin
|
|
// start of frame
|
|
out_frame_cyc = 1'b1;
|
|
|
|
if (!out_done) begin
|
|
out_ctrl_hdr_next = 1'b1;
|
|
out_ctrl_last_len_next = ctrl_fifo_rd_last_len[AXIS_BYTE_IDX_WIDTH*out_cur_seg +: AXIS_BYTE_IDX_WIDTH];
|
|
out_ctrl_seg_offset_next = out_cur_seg;
|
|
end
|
|
end else if (!out_abort) begin
|
|
// consume null segment
|
|
out_seg_consumed[out_cur_seg] = 1'b1;
|
|
out_seg_consumed_next = out_seg_consumed;
|
|
ctrl_fifo_rd_en = out_seg_consumed;
|
|
|
|
out_seg_offset_next = out_seg_offset_cyc;
|
|
end
|
|
end
|
|
end
|
|
out_frame = out_frame_cyc;
|
|
|
|
if (out_frame && !out_done) begin
|
|
if (shift_out_seg_end[0]) begin
|
|
// last output cycle
|
|
out_frame_cyc = 0;
|
|
out_done = 1;
|
|
|
|
if (shift_out_seg_last[0]) begin
|
|
out_ctrl_last_next = 1'b1;
|
|
end
|
|
|
|
if (out_valid && (out_valid_straddle || shift_out_seg_eop[0]) && m_axis_tready_int) begin
|
|
out_ctrl_en_next = 1'b1;
|
|
out_seg_consumed[out_cur_seg] = 1'b1;
|
|
out_seg_consumed_next = out_seg_consumed;
|
|
ctrl_fifo_rd_en = out_seg_consumed;
|
|
out_frame_next = out_frame_cyc;
|
|
out_seg_offset_next = out_seg_offset_cyc;
|
|
end else begin
|
|
out_abort = 1'b1;
|
|
end
|
|
end else if (output_offset_cyc == AXIS_SEG_CNT-1) begin
|
|
// output full
|
|
out_done = 1;
|
|
|
|
if (out_valid && out_valid_straddle && m_axis_tready_int) begin
|
|
out_ctrl_en_next = 1'b1;
|
|
out_seg_consumed[out_cur_seg] = 1'b1;
|
|
out_seg_consumed_next = out_seg_consumed;
|
|
ctrl_fifo_rd_en = out_seg_consumed;
|
|
out_frame_next = out_frame_cyc;
|
|
out_seg_offset_next = out_seg_offset_cyc;
|
|
end else begin
|
|
out_abort = 1'b1;
|
|
end
|
|
end else begin
|
|
// middle cycle
|
|
|
|
if (out_valid && out_valid_straddle && m_axis_tready_int) begin
|
|
out_seg_consumed[out_cur_seg] = 1'b1;
|
|
end else begin
|
|
out_abort = 1'b1;
|
|
end
|
|
end
|
|
|
|
if (output_offset_cyc == AXIS_SEG_CNT-1) begin
|
|
output_offset_cyc = 0;
|
|
end else begin
|
|
output_offset_cyc = output_offset_cyc + 1;
|
|
end
|
|
end
|
|
|
|
out_cur_seg = out_cur_seg + 1;
|
|
|
|
// shift_out_seg_valid = shift_out_seg_valid >> 1;
|
|
shift_out_seg_valid_straddle = shift_out_seg_valid_straddle >> 1;
|
|
shift_out_seg_sop = shift_out_seg_sop >> 1;
|
|
shift_out_seg_eop = shift_out_seg_eop >> 1;
|
|
shift_out_seg_end = shift_out_seg_end >> 1;
|
|
shift_out_seg_last = shift_out_seg_last >> 1;
|
|
end
|
|
|
|
// construct output
|
|
input_ready_cmb = out_seg_consumed_reg;
|
|
|
|
m_axis_tdata_int = input_data_full >> (SEG_WIDTH*out_ctrl_seg_offset_reg + HDR_WIDTH);
|
|
|
|
if (out_ctrl_last_reg) begin
|
|
m_axis_tkeep_int = {AXIS_KEEP_WIDTH{1'b1}} >> (AXIS_KEEP_WIDTH-1 - out_ctrl_last_len_reg);
|
|
end else begin
|
|
m_axis_tkeep_int = {AXIS_KEEP_WIDTH{1'b1}};
|
|
end
|
|
m_axis_tlast_int = out_ctrl_last_reg;
|
|
|
|
if (out_ctrl_hdr_reg) begin
|
|
axis_tid_next = input_data_full >> (SEG_WIDTH*out_ctrl_seg_offset_reg + 16 + META_ID_OFFSET);
|
|
axis_tdest_next = input_data_full >> (SEG_WIDTH*out_ctrl_seg_offset_reg + 16 + META_DEST_OFFSET);
|
|
axis_tuser_next = input_data_full >> (SEG_WIDTH*out_ctrl_seg_offset_reg + 16 + META_USER_OFFSET);
|
|
end
|
|
|
|
m_axis_tvalid_int = out_ctrl_en_reg;
|
|
|
|
m_axis_tid_int = axis_tid_next;
|
|
m_axis_tdest_int = axis_tdest_next;
|
|
m_axis_tuser_int = axis_tuser_next;
|
|
|
|
if (EXPAND_INPUT) begin
|
|
for (seg = 0; seg < SEG_CNT; seg = seg + 1) begin
|
|
if (input_ready[seg] && input_valid[seg]) begin
|
|
input_data_int_next[SEG_WIDTH*seg +: SEG_WIDTH] = input_data[SEG_WIDTH*seg +: SEG_WIDTH];
|
|
input_valid_int_next[seg] = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
frame_reg <= frame_next;
|
|
last_reg <= last_next;
|
|
extra_cycle_reg <= extra_cycle_next;
|
|
last_straddle_reg <= last_straddle_next;
|
|
seg_cnt_reg <= seg_cnt_next;
|
|
hdr_parity_err_reg <= hdr_parity_err_next;
|
|
|
|
out_frame_reg <= out_frame_next;
|
|
out_seg_offset_reg <= out_seg_offset_next;
|
|
output_offset_reg <= output_offset_next;
|
|
out_seg_consumed_reg <= out_seg_consumed_next;
|
|
|
|
input_data_int_reg <= input_data_int_next;
|
|
input_valid_int_reg <= input_valid_int_next;
|
|
|
|
out_ctrl_en_reg <= out_ctrl_en_next;
|
|
out_ctrl_hdr_reg <= out_ctrl_hdr_next;
|
|
out_ctrl_last_reg <= out_ctrl_last_next;
|
|
out_ctrl_last_len_reg <= out_ctrl_last_len_next;
|
|
out_ctrl_seg_offset_reg <= out_ctrl_seg_offset_next;
|
|
|
|
axis_tid_reg <= axis_tid_next;
|
|
axis_tdest_reg <= axis_tdest_next;
|
|
axis_tuser_reg <= axis_tuser_next;
|
|
|
|
if (rst || fifo_rst_in) begin
|
|
frame_reg <= 1'b0;
|
|
hdr_parity_err_reg <= 1'b0;
|
|
out_frame_reg <= 1'b0;
|
|
out_seg_offset_reg <= 0;
|
|
output_offset_reg <= 0;
|
|
out_seg_consumed_reg <= 0;
|
|
input_valid_int_next <= 1'b0;
|
|
out_ctrl_en_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// output datapath logic
|
|
reg [AXIS_DATA_WIDTH-1:0] m_axis_tdata_reg = {AXIS_DATA_WIDTH{1'b0}};
|
|
reg [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep_reg = {AXIS_KEEP_WIDTH{1'b0}};
|
|
reg m_axis_tvalid_reg = 1'b0;
|
|
reg m_axis_tlast_reg = 1'b0;
|
|
reg [AXIS_ID_WIDTH-1:0] m_axis_tid_reg = {AXIS_ID_WIDTH{1'b0}};
|
|
reg [AXIS_DEST_WIDTH-1:0] m_axis_tdest_reg = {AXIS_DEST_WIDTH{1'b0}};
|
|
reg [AXIS_USER_WIDTH-1:0] m_axis_tuser_reg = {AXIS_USER_WIDTH{1'b0}};
|
|
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
|
|
reg out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
|
|
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXIS_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXIS_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXIS_ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXIS_DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [AXIS_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
|
|
assign m_axis_tready_int = !out_fifo_half_full_reg;
|
|
|
|
assign m_axis_tdata = m_axis_tdata_reg;
|
|
assign m_axis_tkeep = AXIS_KEEP_ENABLE ? m_axis_tkeep_reg : {AXIS_KEEP_WIDTH{1'b1}};
|
|
assign m_axis_tvalid = m_axis_tvalid_reg;
|
|
assign m_axis_tlast = AXIS_LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
|
|
assign m_axis_tid = AXIS_ID_ENABLE ? m_axis_tid_reg : {AXIS_ID_WIDTH{1'b0}};
|
|
assign m_axis_tdest = AXIS_DEST_ENABLE ? m_axis_tdest_reg : {AXIS_DEST_WIDTH{1'b0}};
|
|
assign m_axis_tuser = AXIS_USER_ENABLE ? m_axis_tuser_reg : {AXIS_USER_WIDTH{1'b0}};
|
|
|
|
always @(posedge clk) begin
|
|
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (!out_fifo_full && m_axis_tvalid_int) begin
|
|
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_int;
|
|
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_int;
|
|
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_int;
|
|
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_int;
|
|
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_int;
|
|
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_int;
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin
|
|
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_tvalid_reg <= 1'b1;
|
|
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst || fifo_rst_in) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
m_axis_tvalid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|