verilog-axi

FPGA/verilog-axi

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Alex Forencich 66b20c171b Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

axi.py

Properly handle read bursts in AXI model

2018-08-13 15:12:56 -07:00

test_axi_fifo_delay.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_delay.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd_delay.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd_delay.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_rd.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr_delay.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr_delay.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo_wr.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo.py

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_fifo.v

Add AXI FIFOs and testbenches

2018-08-13 15:31:04 -07:00

test_axi_ram.py

Improve testbench and fix bugs in axi_ram

2018-08-11 22:32:05 -07:00

test_axi_ram.v

Initial commit

2018-07-29 19:04:30 -07:00

test_axi.py

Properly handle read bursts in AXI model

2018-08-13 15:12:56 -07:00