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441 lines
16 KiB
Verilog
441 lines
16 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite crossbar (read)
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*/
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module axil_crossbar_rd #
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(
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// Number of AXI inputs (slave interfaces)
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parameter S_COUNT = 4,
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Number of concurrent operations for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_ACCEPT = {S_COUNT{32'd16}},
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
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// set to zero for default addressing based on M_ADDR_WIDTH
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parameter M_BASE_ADDR = 0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Read connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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parameter M_ISSUE = {M_COUNT{32'd16}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}},
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI lite slave interfaces
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*/
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input wire [S_COUNT*ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [S_COUNT*3-1:0] s_axil_arprot,
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input wire [S_COUNT-1:0] s_axil_arvalid,
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output wire [S_COUNT-1:0] s_axil_arready,
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output wire [S_COUNT*DATA_WIDTH-1:0] s_axil_rdata,
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output wire [S_COUNT*2-1:0] s_axil_rresp,
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output wire [S_COUNT-1:0] s_axil_rvalid,
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input wire [S_COUNT-1:0] s_axil_rready,
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/*
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* AXI lite master interfaces
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*/
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output wire [M_COUNT*ADDR_WIDTH-1:0] m_axil_araddr,
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output wire [M_COUNT*3-1:0] m_axil_arprot,
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output wire [M_COUNT-1:0] m_axil_arvalid,
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input wire [M_COUNT-1:0] m_axil_arready,
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input wire [M_COUNT*DATA_WIDTH-1:0] m_axil_rdata,
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input wire [M_COUNT*2-1:0] m_axil_rresp,
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input wire [M_COUNT-1:0] m_axil_rvalid,
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output wire [M_COUNT-1:0] m_axil_rready
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);
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parameter CL_S_COUNT = $clog2(S_COUNT);
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parameter CL_M_COUNT = $clog2(M_COUNT);
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parameter M_COUNT_P1 = M_COUNT+1;
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parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
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integer i;
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// check configuration
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initial begin
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for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < $clog2(STRB_WIDTH) || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
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$error("Error: value out of range (instance %m)");
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$finish;
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end
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end
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end
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wire [S_COUNT*ADDR_WIDTH-1:0] int_s_axil_araddr;
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wire [S_COUNT*3-1:0] int_s_axil_arprot;
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wire [S_COUNT-1:0] int_s_axil_arvalid;
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wire [S_COUNT-1:0] int_s_axil_arready;
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wire [S_COUNT*M_COUNT-1:0] int_axil_arvalid;
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wire [M_COUNT*S_COUNT-1:0] int_axil_arready;
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wire [M_COUNT*DATA_WIDTH-1:0] int_m_axil_rdata;
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wire [M_COUNT*2-1:0] int_m_axil_rresp;
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wire [M_COUNT-1:0] int_m_axil_rvalid;
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wire [M_COUNT-1:0] int_m_axil_rready;
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wire [M_COUNT*S_COUNT-1:0] int_axil_rvalid;
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wire [S_COUNT*M_COUNT-1:0] int_axil_rready;
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generate
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genvar m, n;
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for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
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// response routing FIFO
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localparam FIFO_ADDR_WIDTH = $clog2(S_ACCEPT[m*32 +: 32])+1;
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reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [CL_M_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg fifo_decerr[(2**FIFO_ADDR_WIDTH)-1:0];
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wire [CL_M_COUNT-1:0] fifo_wr_select;
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wire fifo_wr_decerr;
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wire fifo_wr_en;
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reg [CL_M_COUNT-1:0] fifo_rd_select_reg = 0;
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reg fifo_rd_decerr_reg = 0;
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reg fifo_rd_valid_reg = 0;
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wire fifo_rd_en;
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reg fifo_half_full_reg = 1'b0;
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wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
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integer i;
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initial begin
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for (i = 0; i < 2**FIFO_ADDR_WIDTH; i = i + 1) begin
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fifo_select[i] = 0;
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fifo_decerr[i] = 0;
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end
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end
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always @(posedge clk) begin
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if (fifo_wr_en) begin
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fifo_select[fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= fifo_wr_select;
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fifo_decerr[fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= fifo_wr_decerr;
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fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
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end
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fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
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if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
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fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
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fifo_rd_valid_reg <= 1'b1;
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fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
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end
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fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_ADDR_WIDTH-1);
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if (rst) begin
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fifo_wr_ptr_reg <= 0;
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fifo_rd_ptr_reg <= 0;
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fifo_rd_valid_reg <= 1'b0;
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end
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end
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// address decode and admission control
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wire [CL_M_COUNT-1:0] a_select;
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wire m_axil_avalid;
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wire m_axil_aready;
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wire [CL_M_COUNT-1:0] m_rc_select;
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wire m_rc_decerr;
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wire m_rc_valid;
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wire m_rc_ready;
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axil_crossbar_addr #(
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.S(m),
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.S_COUNT(S_COUNT),
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.M_COUNT(M_COUNT),
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.ADDR_WIDTH(ADDR_WIDTH),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_WIDTH(M_ADDR_WIDTH),
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.M_CONNECT(M_CONNECT),
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.M_SECURE(M_SECURE),
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.WC_OUTPUT(0)
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)
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addr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Address input
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*/
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.s_axil_aaddr(int_s_axil_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
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.s_axil_aprot(int_s_axil_arprot[m*3 +: 3]),
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.s_axil_avalid(int_s_axil_arvalid[m]),
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.s_axil_aready(int_s_axil_arready[m]),
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/*
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* Address output
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*/
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.m_select(a_select),
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.m_axil_avalid(m_axil_avalid),
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.m_axil_aready(m_axil_aready),
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/*
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* Write command output
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*/
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.m_wc_select(),
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.m_wc_decerr(),
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.m_wc_valid(),
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.m_wc_ready(1'b1),
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/*
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* Response command output
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*/
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.m_rc_select(m_rc_select),
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.m_rc_decerr(m_rc_decerr),
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.m_rc_valid(m_rc_valid),
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.m_rc_ready(m_rc_ready)
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);
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assign int_axil_arvalid[m*M_COUNT +: M_COUNT] = m_axil_avalid << a_select;
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assign m_axil_aready = int_axil_arready[a_select*S_COUNT+m];
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// response handling
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assign fifo_wr_select = m_rc_select;
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assign fifo_wr_decerr = m_rc_decerr;
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assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg;
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assign m_rc_ready = !fifo_half_full_reg;
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// write response handling
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wire [CL_M_COUNT-1:0] r_select = M_COUNT > 1 ? fifo_rd_select_reg : 0;
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wire r_decerr = fifo_rd_decerr_reg;
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wire r_valid = fifo_rd_valid_reg;
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// read response mux
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wire [DATA_WIDTH-1:0] m_axil_rdata_mux = r_decerr ? {DATA_WIDTH{1'b0}} : int_m_axil_rdata[r_select*DATA_WIDTH +: DATA_WIDTH];
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wire [1:0] m_axil_rresp_mux = r_decerr ? 2'b11 : int_m_axil_rresp[r_select*2 +: 2];
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wire m_axil_rvalid_mux = (r_decerr ? 1'b1 : int_axil_rvalid[r_select*S_COUNT+m]) && r_valid;
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wire m_axil_rready_mux;
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assign int_axil_rready[m*M_COUNT +: M_COUNT] = (r_valid && m_axil_rready_mux) << r_select;
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assign fifo_rd_en = m_axil_rvalid_mux && m_axil_rready_mux && r_valid;
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// S side register
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axil_register_rd #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
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.R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
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)
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reg_inst (
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.clk(clk),
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.rst(rst),
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.s_axil_araddr(s_axil_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
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.s_axil_arprot(s_axil_arprot[m*3 +: 3]),
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.s_axil_arvalid(s_axil_arvalid[m]),
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.s_axil_arready(s_axil_arready[m]),
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.s_axil_rdata(s_axil_rdata[m*DATA_WIDTH +: DATA_WIDTH]),
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.s_axil_rresp(s_axil_rresp[m*2 +: 2]),
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.s_axil_rvalid(s_axil_rvalid[m]),
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.s_axil_rready(s_axil_rready[m]),
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.m_axil_araddr(int_s_axil_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
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.m_axil_arprot(int_s_axil_arprot[m*3 +: 3]),
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.m_axil_arvalid(int_s_axil_arvalid[m]),
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.m_axil_arready(int_s_axil_arready[m]),
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.m_axil_rdata(m_axil_rdata_mux),
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.m_axil_rresp(m_axil_rresp_mux),
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.m_axil_rvalid(m_axil_rvalid_mux),
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.m_axil_rready(m_axil_rready_mux)
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);
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end // s_ifaces
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for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
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// response routing FIFO
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localparam FIFO_ADDR_WIDTH = $clog2(M_ISSUE[n*32 +: 32])+1;
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reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [CL_S_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0];
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wire [CL_S_COUNT-1:0] fifo_wr_select;
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wire fifo_wr_en;
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wire fifo_rd_en;
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reg fifo_half_full_reg = 1'b0;
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wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
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integer i;
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initial begin
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for (i = 0; i < 2**FIFO_ADDR_WIDTH; i = i + 1) begin
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fifo_select[i] = 0;
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end
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end
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always @(posedge clk) begin
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if (fifo_wr_en) begin
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fifo_select[fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= fifo_wr_select;
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fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
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end
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if (fifo_rd_en) begin
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fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
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end
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fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_ADDR_WIDTH-1);
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if (rst) begin
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fifo_wr_ptr_reg <= 0;
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fifo_rd_ptr_reg <= 0;
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end
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end
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// address arbitration
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wire [S_COUNT-1:0] a_request;
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wire [S_COUNT-1:0] a_acknowledge;
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wire [S_COUNT-1:0] a_grant;
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wire a_grant_valid;
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wire [CL_S_COUNT-1:0] a_grant_encoded;
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arbiter #(
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.PORTS(S_COUNT),
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.ARB_TYPE_ROUND_ROBIN(1),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.ARB_LSB_HIGH_PRIORITY(1)
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)
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a_arb_inst (
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.clk(clk),
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.rst(rst),
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.request(a_request),
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.acknowledge(a_acknowledge),
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.grant(a_grant),
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.grant_valid(a_grant_valid),
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.grant_encoded(a_grant_encoded)
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);
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// address mux
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wire [ADDR_WIDTH-1:0] s_axil_araddr_mux = int_s_axil_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
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wire [2:0] s_axil_arprot_mux = int_s_axil_arprot[a_grant_encoded*3 +: 3];
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wire s_axil_arvalid_mux = int_axil_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
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wire s_axil_arready_mux;
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assign int_axil_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axil_arready_mux) << a_grant_encoded;
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for (m = 0; m < S_COUNT; m = m + 1) begin
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assign a_request[m] = int_axil_arvalid[m*M_COUNT+n] && !a_grant[m] && !fifo_half_full_reg;
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assign a_acknowledge[m] = a_grant[m] && int_axil_arvalid[m*M_COUNT+n] && s_axil_arready_mux;
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end
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assign fifo_wr_select = a_grant_encoded;
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assign fifo_wr_en = s_axil_arvalid_mux && s_axil_arready_mux && a_grant_valid;
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// read response forwarding
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wire [CL_S_COUNT-1:0] r_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]] : 0;
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assign int_axil_rvalid[n*S_COUNT +: S_COUNT] = int_m_axil_rvalid[n] << r_select;
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assign int_m_axil_rready[n] = int_axil_rready[r_select*M_COUNT+n];
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assign fifo_rd_en = int_m_axil_rvalid[n] && int_m_axil_rready[n];
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// M side register
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axil_register_rd #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
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.R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
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)
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reg_inst (
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.clk(clk),
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.rst(rst),
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.s_axil_araddr(s_axil_araddr_mux),
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.s_axil_arprot(s_axil_arprot_mux),
|
|
.s_axil_arvalid(s_axil_arvalid_mux),
|
|
.s_axil_arready(s_axil_arready_mux),
|
|
.s_axil_rdata(int_m_axil_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
|
|
.s_axil_rresp(int_m_axil_rresp[n*2 +: 2]),
|
|
.s_axil_rvalid(int_m_axil_rvalid[n]),
|
|
.s_axil_rready(int_m_axil_rready[n]),
|
|
.m_axil_araddr(m_axil_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
|
|
.m_axil_arprot(m_axil_arprot[n*3 +: 3]),
|
|
.m_axil_arvalid(m_axil_arvalid[n]),
|
|
.m_axil_arready(m_axil_arready[n]),
|
|
.m_axil_rdata(m_axil_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
|
|
.m_axil_rresp(m_axil_rresp[n*2 +: 2]),
|
|
.m_axil_rvalid(m_axil_rvalid[n]),
|
|
.m_axil_rready(m_axil_rready[n])
|
|
);
|
|
end // m_ifaces
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|