verilog-axi/vivado at 99ff2e81b74eca0d623942b3f26395d1c577ea77 - verilog-axi - Gitea: Git with a cup of tea

FPGA/verilog-axi

mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-28 07:02:56 +08:00

History

Alex Forencich f521fb6435 Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2023-01-17 13:40:36 -08:00

..

axil_cdc.tcl

Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis

2023-01-17 13:40:36 -08:00