FPGA/verilog-axi
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verilog-axi/rtl
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Alex Forencich a60e1f726f Fix use before define
2019-03-18 14:02:10 -07:00
..
arbiter.v
Add arbiter and priority encoder modules
2018-08-22 21:50:31 -07:00
axi_adapter_rd.v
Change cycle to segment, clean up parameters
2018-12-03 12:52:00 -08:00
axi_adapter_wr.v
Change cycle to segment, clean up parameters
2018-12-03 12:52:00 -08:00
axi_adapter.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_cdma_desc_mux.v
Add AXI DMA and CDMA descriptor mux modules
2019-02-25 15:44:10 -08:00
axi_cdma.v
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
axi_crossbar_addr.v
Fix use before define
2019-03-12 13:15:11 -07:00
axi_crossbar_rd.v
Fix bug
2019-03-05 22:20:44 -08:00
axi_crossbar_wr.v
Fix use before define
2019-03-12 13:15:11 -07:00
axi_crossbar.v
Add AXI nonblocking crossbar interconnect module and testbench
2019-02-25 18:37:46 -08:00
axi_dma_desc_mux.v
Incorrect signals
2019-02-25 20:37:55 -08:00
axi_dma_rd.v
Minor reorganization
2018-12-06 17:19:30 -08:00
axi_dma_wr.v
Ensure transfer is terminated at the end of the input frame
2019-03-13 14:48:05 -07:00
axi_dma.v
Add AXI DMA module and testbench
2018-12-27 14:21:06 -08:00
axi_dp_ram.v
Pass through more signals in AXI RAM interfaces
2019-02-26 01:25:03 -08:00
axi_fifo_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_fifo_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_fifo.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_interconnect.v
Fix use before define
2019-03-18 14:02:10 -07:00
axi_ram_rd_if.v
Pass through more signals in AXI RAM interfaces
2019-02-26 01:25:03 -08:00
axi_ram_wr_if.v
Pass through more signals in AXI RAM interfaces
2019-02-26 01:25:03 -08:00
axi_ram_wr_rd_if.v
Pass through more signals in AXI RAM interfaces
2019-02-26 01:25:03 -08:00
axi_ram.v
Add optional output pipeline register to AXI RAM module
2018-11-27 01:17:31 -08:00
axi_register_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_register_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_adapter_rd.v
Change cycle to segment, clean up parameters
2018-12-06 18:32:46 -08:00
axil_adapter_wr.v
Change cycle to segment, clean up parameters
2018-12-06 18:32:46 -08:00
axil_adapter.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_dp_ram.v
Add AXI lite dual-port RAM module and testbench
2019-01-17 17:48:23 -08:00
axil_interconnect.v
Fix use before define
2019-03-18 14:02:10 -07:00
axil_ram.v
Remove unnecessary reset
2019-01-17 17:09:55 -08:00
axil_register_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_register_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
priority_encoder.v
Add arbiter and priority encoder modules
2018-08-22 21:50:31 -07:00