FPGA/verilog-axi
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verilog-axi/rtl
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Alex Forencich b4bdfb6542 Add FIFO output register in AXI lite crossbar modules
2021-11-06 15:20:19 -07:00
..
arbiter.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_adapter_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_adapter_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_adapter.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_axil_adapter_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_axil_adapter_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_axil_adapter.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_cdma_desc_mux.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_cdma.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_crossbar_addr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_crossbar_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_crossbar_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_crossbar_wrap.py
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_crossbar.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_dma_desc_mux.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_dma_rd.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-04 20:43:13 -07:00
axi_dma_wr.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-04 20:43:13 -07:00
axi_dma.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_dp_ram.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_fifo_rd.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-04 20:43:13 -07:00
axi_fifo_wr.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-04 20:43:13 -07:00
axi_fifo.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_interconnect_wrap.py
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_interconnect.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_ram_rd_if.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_ram_wr_if.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_ram_wr_rd_if.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_ram.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_register_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_register_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axi_register.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_adapter_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_adapter_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_adapter.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_cdc_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_cdc_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_cdc.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_crossbar_addr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_crossbar_rd.v
Add FIFO output register in AXI lite crossbar modules
2021-11-06 15:20:19 -07:00
axil_crossbar_wr.v
Add FIFO output register in AXI lite crossbar modules
2021-11-06 15:20:19 -07:00
axil_crossbar_wrap.py
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_crossbar.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_dp_ram.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_interconnect_wrap.py
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_interconnect.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_ram.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_reg_if_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_reg_if_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_reg_if.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_register_rd.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_register_wr.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
axil_register.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00
priority_encoder.v
Add default_nettype none and resetall directives
2021-10-20 15:36:04 -07:00