mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-28 07:02:56 +08:00
208 lines
6.9 KiB
Python
208 lines
6.9 KiB
Python
"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiReadBus, AxiRamRead
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from cocotbext.axi import AxiStreamBus, AxiStreamSink
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from cocotbext.axi.stream import define_stream
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DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
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signals=["addr", "len", "tag", "valid", "ready"],
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optional_signals=["id", "dest", "user"]
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)
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DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
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signals=["tag", "valid"],
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optional_signals=["len", "id", "dest", "user"]
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)
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.fork(Clock(dut.clk, 10, units="ns").start())
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# read interface
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self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst)
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self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst)
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self.read_data_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis_read_data"), dut.clk, dut.rst)
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# AXI interface
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self.axi_ram = AxiRamRead(AxiReadBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
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dut.enable.setimmediatevalue(0)
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def set_idle_generator(self, generator=None):
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if generator:
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self.read_desc_source.set_pause_generator(generator())
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self.axi_ram.r_channel.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.read_data_sink.set_pause_generator(generator())
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self.axi_ram.ar_channel.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_width = tb.axi_ram.byte_width
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step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_width
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tag_count = 2**len(tb.read_desc_source.bus.tag)
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cur_tag = 1
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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dut.enable <= 1
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for length in list(range(1, byte_width*4+1))+[128]:
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for offset in list(range(0, byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write(addr-128, b'\xaa'*(len(test_data)+256))
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tb.axi_ram.write(addr, test_data)
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tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
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desc = DescTransaction(addr=addr, len=len(test_data), tag=cur_tag, id=cur_tag)
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await tb.read_desc_source.send(desc)
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status = await tb.read_desc_status_sink.recv()
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read_data = await tb.read_data_sink.recv()
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tb.log.info("status: %s", status)
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tb.log.info("read_data: %s", read_data)
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assert int(status.tag) == cur_tag
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assert read_data.tdata == test_data
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assert read_data.tid == cur_tag
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cur_tag = (cur_tag + 1) % tag_count
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test_read)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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@pytest.mark.parametrize("unaligned", [0, 1])
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@pytest.mark.parametrize("axi_data_width", [8, 16, 32])
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def test_axi_dma_rd(request, axi_data_width, unaligned):
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dut = "axi_dma_rd"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.v"),
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]
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parameters = {}
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axis_data_width = axi_data_width
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parameters['AXI_DATA_WIDTH'] = axi_data_width
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parameters['AXI_ADDR_WIDTH'] = 16
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parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
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parameters['AXI_ID_WIDTH'] = 8
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parameters['AXI_MAX_BURST_LEN'] = 16
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parameters['AXIS_DATA_WIDTH'] = axis_data_width
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parameters['AXIS_KEEP_ENABLE'] = int(parameters['AXIS_DATA_WIDTH'] > 8)
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parameters['AXIS_KEEP_WIDTH'] = parameters['AXIS_DATA_WIDTH'] // 8
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parameters['AXIS_LAST_ENABLE'] = 1
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parameters['AXIS_ID_ENABLE'] = 1
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parameters['AXIS_ID_WIDTH'] = 8
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parameters['AXIS_DEST_ENABLE'] = 0
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parameters['AXIS_DEST_WIDTH'] = 8
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parameters['AXIS_USER_ENABLE'] = 1
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parameters['AXIS_USER_WIDTH'] = 1
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parameters['LEN_WIDTH'] = 20
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parameters['TAG_WIDTH'] = 8
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parameters['ENABLE_SG'] = 0
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parameters['ENABLE_UNALIGNED'] = unaligned
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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