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verilog-axi/rtl
History
Alex Forencich c1f31e537e Remove unnecessary wait state when output is ready
2020-08-17 00:13:02 -07:00
..
arbiter.v
Add arbiter and priority encoder modules
2018-08-22 21:50:31 -07:00
axi_adapter_rd.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_adapter_wr.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_axil_adapter_rd.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_axil_adapter_wr.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_axil_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_cdma_desc_mux.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_cdma.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_crossbar_addr.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_crossbar_rd.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_crossbar_wr.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_crossbar.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_dma_desc_mux.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_dma_rd.v
Bypass check when unneeded
2019-10-30 22:57:56 -07:00
axi_dma_wr.v
Bypass check when unneeded
2019-10-30 22:57:56 -07:00
axi_dma.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_dp_ram.v
Fix backpressure bug
2020-04-12 23:33:15 -07:00
axi_fifo_rd.v
Remove unnecessary wait state when output is ready
2020-08-17 00:13:02 -07:00
axi_fifo_wr.v
Remove unnecessary wait state when output is ready
2020-08-17 00:13:02 -07:00
axi_fifo.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_interconnect.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_ram_rd_if.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_ram_wr_if.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_ram_wr_rd_if.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_ram.v
Use correct RAM size for initialization
2019-11-24 15:38:10 -08:00
axi_register_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_register_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_register.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_adapter_rd.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axil_adapter_wr.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axil_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_dp_ram.v
Use correct RAM size for initialization
2019-11-24 15:38:10 -08:00
axil_interconnect.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axil_ram.v
Use correct RAM size for initialization
2019-11-24 15:38:10 -08:00
axil_register_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_register_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_register.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
priority_encoder.v
Update priority encoder
2019-07-24 14:22:47 -07:00