mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
362 lines
13 KiB
Verilog
362 lines
13 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 DMA
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*/
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module axi_dma #
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(
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// Width of AXI data bus in bits
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parameter AXI_DATA_WIDTH = 32,
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// Width of AXI address bus in bits
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parameter AXI_ADDR_WIDTH = 16,
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// Width of AXI wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Maximum AXI burst length to generate
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parameter AXI_MAX_BURST_LEN = 16,
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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// Use AXI stream tkeep signal
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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// Use AXI stream tlast signal
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parameter AXIS_LAST_ENABLE = 1,
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// Propagate AXI stream tid signal
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parameter AXIS_ID_ENABLE = 0,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// Propagate AXI stream tdest signal
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parameter AXIS_DEST_ENABLE = 0,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// Propagate AXI stream tuser signal
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parameter AXIS_USER_ENABLE = 1,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1,
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// Width of length field
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parameter LEN_WIDTH = 20,
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// Width of tag field
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parameter TAG_WIDTH = 8,
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// Enable support for scatter/gather DMA
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// (multiple descriptors per AXI stream frame)
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parameter ENABLE_SG = 0,
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// Enable support for unaligned transfers
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parameter ENABLE_UNALIGNED = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI read descriptor input
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*/
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_addr,
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input wire [LEN_WIDTH-1:0] s_axis_read_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_read_desc_tag,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user,
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input wire s_axis_read_desc_valid,
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output wire s_axis_read_desc_ready,
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/*
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* AXI read descriptor status output
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*/
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output wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
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output wire [3:0] m_axis_read_desc_status_error,
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output wire m_axis_read_desc_status_valid,
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/*
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* AXI stream read data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
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output wire m_axis_read_data_tvalid,
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input wire m_axis_read_data_tready,
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output wire m_axis_read_data_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
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/*
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* AXI write descriptor input
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*/
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input wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_addr,
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input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input wire s_axis_write_desc_valid,
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output wire s_axis_write_desc_ready,
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/*
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* AXI write descriptor status output
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*/
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output wire [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
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output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
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output wire [3:0] m_axis_write_desc_status_error,
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output wire m_axis_write_desc_status_valid,
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/*
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* AXI stream write data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
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input wire s_axis_write_data_tvalid,
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output wire s_axis_write_data_tready,
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input wire s_axis_write_data_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
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/*
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* AXI master interface
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*/
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready,
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/*
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* Configuration
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*/
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input wire read_enable,
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input wire write_enable,
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input wire write_abort
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);
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axi_dma_rd #(
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH(AXIS_USER_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.ENABLE_SG(ENABLE_SG),
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.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
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)
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axi_dma_rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI read descriptor input
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*/
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.s_axis_read_desc_addr(s_axis_read_desc_addr),
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.s_axis_read_desc_len(s_axis_read_desc_len),
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.s_axis_read_desc_tag(s_axis_read_desc_tag),
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.s_axis_read_desc_id(s_axis_read_desc_id),
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.s_axis_read_desc_dest(s_axis_read_desc_dest),
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.s_axis_read_desc_user(s_axis_read_desc_user),
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.s_axis_read_desc_valid(s_axis_read_desc_valid),
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.s_axis_read_desc_ready(s_axis_read_desc_ready),
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/*
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* AXI read descriptor status output
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*/
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.m_axis_read_desc_status_tag(m_axis_read_desc_status_tag),
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.m_axis_read_desc_status_error(m_axis_read_desc_status_error),
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.m_axis_read_desc_status_valid(m_axis_read_desc_status_valid),
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/*
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* AXI stream read data output
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*/
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.m_axis_read_data_tdata(m_axis_read_data_tdata),
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.m_axis_read_data_tkeep(m_axis_read_data_tkeep),
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.m_axis_read_data_tvalid(m_axis_read_data_tvalid),
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.m_axis_read_data_tready(m_axis_read_data_tready),
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.m_axis_read_data_tlast(m_axis_read_data_tlast),
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.m_axis_read_data_tid(m_axis_read_data_tid),
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.m_axis_read_data_tdest(m_axis_read_data_tdest),
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.m_axis_read_data_tuser(m_axis_read_data_tuser),
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/*
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* AXI master interface
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*/
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.m_axi_arid(m_axi_arid),
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.m_axi_araddr(m_axi_araddr),
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.m_axi_arlen(m_axi_arlen),
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.m_axi_arsize(m_axi_arsize),
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.m_axi_arburst(m_axi_arburst),
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.m_axi_arlock(m_axi_arlock),
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.m_axi_arcache(m_axi_arcache),
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.m_axi_arprot(m_axi_arprot),
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.m_axi_arvalid(m_axi_arvalid),
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.m_axi_arready(m_axi_arready),
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.m_axi_rid(m_axi_rid),
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.m_axi_rdata(m_axi_rdata),
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.m_axi_rresp(m_axi_rresp),
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.m_axi_rlast(m_axi_rlast),
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.m_axi_rvalid(m_axi_rvalid),
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.m_axi_rready(m_axi_rready),
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/*
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* Configuration
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*/
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.enable(read_enable)
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);
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axi_dma_wr #(
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH(AXIS_USER_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.ENABLE_SG(ENABLE_SG),
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.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
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)
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axi_dma_wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI write descriptor input
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*/
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.s_axis_write_desc_addr(s_axis_write_desc_addr),
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.s_axis_write_desc_len(s_axis_write_desc_len),
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.s_axis_write_desc_tag(s_axis_write_desc_tag),
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.s_axis_write_desc_valid(s_axis_write_desc_valid),
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.s_axis_write_desc_ready(s_axis_write_desc_ready),
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/*
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* AXI write descriptor status output
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*/
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.m_axis_write_desc_status_len(m_axis_write_desc_status_len),
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.m_axis_write_desc_status_tag(m_axis_write_desc_status_tag),
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.m_axis_write_desc_status_id(m_axis_write_desc_status_id),
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.m_axis_write_desc_status_dest(m_axis_write_desc_status_dest),
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.m_axis_write_desc_status_user(m_axis_write_desc_status_user),
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.m_axis_write_desc_status_error(m_axis_write_desc_status_error),
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.m_axis_write_desc_status_valid(m_axis_write_desc_status_valid),
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/*
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* AXI stream write data input
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*/
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.s_axis_write_data_tdata(s_axis_write_data_tdata),
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.s_axis_write_data_tkeep(s_axis_write_data_tkeep),
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.s_axis_write_data_tvalid(s_axis_write_data_tvalid),
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.s_axis_write_data_tready(s_axis_write_data_tready),
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.s_axis_write_data_tlast(s_axis_write_data_tlast),
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.s_axis_write_data_tid(s_axis_write_data_tid),
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.s_axis_write_data_tdest(s_axis_write_data_tdest),
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.s_axis_write_data_tuser(s_axis_write_data_tuser),
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/*
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* AXI master interface
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*/
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.m_axi_awid(m_axi_awid),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready),
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/*
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* Configuration
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*/
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.enable(write_enable),
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.abort(write_abort)
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);
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endmodule
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`resetall
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