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89 lines
3.1 KiB
Verilog
89 lines
3.1 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Priority encoder module
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*/
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module priority_encoder #
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(
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parameter WIDTH = 4,
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// LSB priority selection
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parameter LSB_HIGH_PRIORITY = 0
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)
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(
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input wire [WIDTH-1:0] input_unencoded,
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output wire output_valid,
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output wire [$clog2(WIDTH)-1:0] output_encoded,
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output wire [WIDTH-1:0] output_unencoded
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);
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parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;
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parameter W = 2**LEVELS;
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// pad input to even power of two
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wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};
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wire [W/2-1:0] stage_valid[LEVELS-1:0];
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wire [W/2-1:0] stage_enc[LEVELS-1:0];
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generate
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genvar l, n;
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// process input bits; generate valid bit and encoded bit for each pair
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for (n = 0; n < W/2; n = n + 1) begin : loop_in
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assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
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if (LSB_HIGH_PRIORITY) begin
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// bit 0 is highest priority
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assign stage_enc[0][n] = !input_padded[n*2+0];
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[0][n] = input_padded[n*2+1];
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end
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end
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// compress down to single valid bit and encoded bus
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for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
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for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
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assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
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if (LSB_HIGH_PRIORITY) begin
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// bit 0 is highest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
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end
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end
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end
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endgenerate
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assign output_valid = stage_valid[LEVELS-1];
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assign output_encoded = stage_enc[LEVELS-1];
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assign output_unencoded = 1 << output_encoded;
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endmodule
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