FPGA/verilog-ethernet - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00

1 line

25 B

Python

Raw Normal View History

Replace axis_ep.py with symlink

2015-05-07 19:11:31 -07:00

../lib/axis/tb/axis_ep.py