FPGA/verilog-ethernet - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00

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Add ML605 SGMII design

2017-07-22 11:07:23 -07:00

../lib/eth/tb/ip_ep.py