FPGA/verilog-ethernet - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00

1 line

25 B

Python

Raw Normal View History

Add ML605 RGMII example design

2017-05-31 20:24:43 -07:00

../lib/eth/tb/rgmii_ep.py