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29 lines
757 B
Markdown
29 lines
757 B
Markdown
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# Verilog Ethernet KC705 Example Design
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## Introduction
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This example design targets the Xilinx KC705 FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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Configure the PHY for GMII by placing J29 and J30 across pins 1 and 2 and
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opening J64.
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FPGA: XC7K325T-2FFG900C
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PHY: Marvell 88E1111
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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## How to test
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Run make program to program the KC705 board with Vivado. Then run netcat -u
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192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered
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into netcat will be echoed back after pressing enter.
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