FPGA/verilog-ethernet - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00

1 line

23 B

Python

Raw Normal View History

Add example design for VCU108 board

2016-07-05 11:52:28 -04:00

../lib/eth/tb/udp_ep.py