FPGA/verilog-ethernet - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00

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Add ML605 RGMII example design

2017-05-31 20:24:43 -07:00

../lib/eth/tb/axis_ep.py