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26 lines
711 B
Markdown
26 lines
711 B
Markdown
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# Verilog Ethernet Cyclone 10 LP Example Design
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## Introduction
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This example design targets the Intel Cyclone 10 LP FPGA development board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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FPGA: 5SGXEA7N2F45C2
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PHY: Intel XWAY PHY11G PEF7071
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## How to build
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Run make to build. Ensure that the Altera Quartus toolchain components are
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in PATH.
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## How to test
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Run make program to program the board with the Altera software. Then run
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netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any
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text entered into netcat will be echoed back after pressing enter.
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