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120 lines
4.3 KiB
Markdown
120 lines
4.3 KiB
Markdown
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# Verilog Ethernet Components Readme
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For more information and updates: http://alexforencich.com/wiki/en/verilog/ethernet/start
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GitHub repository: https://github.com/alexforencich/verilog-ethernet
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## Introduction
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Collection of Ethernet-related components for both gigabit and 10G packet
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processing (8 bit and 64 bit datapaths). Includes modules for handling
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Ethernet frames as well as IP, UDP, and ARP and the components for
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constructing a complete UDP/IP stack. Includes full MyHDL testbench with
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intelligent bus cosimulation endpoints.
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## Documentation
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## eth_axis_rx module
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Ethernet frame receiver.
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## eth_axis_rx_64 module
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Ethernet frame receiver with 64 bit datapath for 10G Ethernet.
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## eth_axis_tx module
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Ethernet frame transmitter.
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## eth_axis_tx_64 module
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Ethernet frame transmitter with 64 bit datapath for 10G Ethernet.
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### Common signals
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tdata : Data (width generally DATA_WIDTH)
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tkeep : Data word valid (width generally KEEP_WIDTH, present on _64 modules)
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tvalid : Data valid
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tready : Sink ready
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tlast : End-of-frame
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tuser : Bad frame (valid with tlast & tvalid)
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### Source Files
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rtl/arbiter.v : General-purpose parametrizable arbiter
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rtl/eth_axis_rx.v : Ethernet frame receiver
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rtl/eth_axis_rx_64.v : Ethernet frame receiver (64 bit)
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rtl/eth_axis_tx.v : Ethernet frame transmitter
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rtl/eth_axis_tx_64.v : Ethernet frame transmitter (64 bit)
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### AXI Stream Interface Example
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two byte transfer with sink pause after each byte
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__ __ __ __ __ __ __ __ __
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clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
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_____ _________________
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tdata XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX
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_____ _________________
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tkeep XXXXXXXXX_K0__X_K1______________XXXXXXXXXXXXXXXXXXXXXXXX
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_______________________
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tvalid ________/ \_______________________
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______________ _____ ___________
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tready \___________/ \___________/
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_________________
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tlast ______________/ \_______________________
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tuser ________________________________________________________
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two back-to-back packets, no pauses
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__ __ __ __ __ __ __ __ __
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clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
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_____ _____ _____ _____ _____ _____
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tdata XXXXXXXXX_A0__X_A1__X_A2__X_B0__X_B1__X_B2__XXXXXXXXXXXX
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_____ _____ _____ _____ _____ _____
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tkeep XXXXXXXXX_K0__X_K1__X_K2__X_K0__X_K1__X_K2__XXXXXXXXXXXX
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___________________________________
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tvalid ________/ \___________
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________________________________________________________
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tready
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_____ _____
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tlast ____________________/ \___________/ \___________
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tuser ________________________________________________________
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bad frame
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__ __ __ __ __ __
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clk __/ \__/ \__/ \__/ \__/ \__/ \__
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_____ _____ _____
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tdata XXXXXXXXX_A0__X_A1__X_A2__XXXXXXXXXXXX
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_____ _____ _____
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tkeep XXXXXXXXX_K0__X_K1__X_K2__XXXXXXXXXXXX
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_________________
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tvalid ________/ \___________
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______________________________________
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tready
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_____
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tlast ____________________/ \___________
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_____
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tuser ____________________/ \___________
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## Testing
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Running the included testbenches requires MyHDL and Icarus Verilog. Make sure
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that myhdl.vpi is installed properly for cosimulation to work correctly. The
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testbenches can be run with a Python test runner like nose or py.test, or the
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individual test scripts can be run with python directly.
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### Testbench Files
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tb/arp_ep.py : MyHDL ARP frame endpoints
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tb/axis_ep.py : MyHDL AXI Stream endpoints
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tb/eth_ep.py : MyHDL Ethernet frame endpoints
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tb/ip_ep.py : MyHDL IP frame endpoints
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tb/udp_ep.py : MyHDL UDP frame endpoints
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