mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
7 lines
33 B
Plaintext
7 lines
33 B
Plaintext
|
*~
|
||
|
|
*.lxt
|
||
|
|
*.pyc
|
||
|
|
*.vvp
|
||
|
|
*.kate-swp
|
||
|
|
|