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https://github.com/alexforencich/verilog-ethernet.git
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Simplify IFG count handling
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@ -186,12 +186,6 @@ class XGMIISource(object):
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if name is not None:
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print("[%s] Sending frame %s" % (name, repr(frame)))
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if ifg_cnt >= 4:
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deficit_idle_cnt = ifg_cnt - 4
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else:
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deficit_idle_cnt = ifg_cnt
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ifg_cnt = 0
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assert len(dl) > 0
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assert dl[0] == 0x55
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dl[0] = 0xfb
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@ -201,11 +195,15 @@ class XGMIISource(object):
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d = 0
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c = 0
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if ifg_cnt > 0:
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if bw == 8 and ifg_cnt >= 4:
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ifg_cnt = max(ifg_cnt-4, 0)
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k = 4
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d = 0x07070707
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c = 0xf
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deficit_idle_cnt = ifg_cnt
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ifg_cnt = 0
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for i in range(k,bw):
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if len(dl) > 0:
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d |= dl.pop(0) << (8*i)
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