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Fix signal width

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This commit is contained in:
Alex Forencich 2016-07-13 12:21:37 -04:00
parent 61d41789d7
commit 018b3b2691
1 changed files with 1 additions and 1 deletions
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example/VCU108/fpga_1g/tb/test_fpga_core.py
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@ -147,7 +147,7 @@ def bench():
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[3:])
sw = Signal(intbv(0)[4:])
phy_gmii_clk = Signal(bool(0))
phy_gmii_rst = Signal(bool(0))
phy_gmii_rxd = Signal(intbv(0)[8:])