mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
Switch out Xilinx PHY core in ADM-PCIE-9V3 example design
This commit is contained in:
Alex Forencich
parent
2e29aea857
commit
0bbe062c66
@ -14,6 +14,13 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
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@ -42,7 +49,6 @@ XDC_FILES = fpga.xdc
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# IP
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XCI_FILES += ip/gtwizard_ultrascale_0.xci
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XCI_FILES += ip/ten_gig_eth_pcs_pma_0.xci
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include ../common/vivado.mk
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@ -12,6 +12,7 @@
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_ENABLE">"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000"</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_SCALING_FACTOR">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CPLL_VCO_FREQUENCY">2578.125</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_COMMON_USRCLK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FORCE_COMMONS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FREERUN_FREQUENCY">125</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_REV">67</spirit:configurableElementValue>
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@ -103,6 +104,7 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE">X0Y19 X0Y18 X0Y17 X0Y16 X0Y15 X0Y14 X0Y13 X0Y12</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">gtwizard_ultrascale_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_LOC_XDC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_USRCLK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_OPTIONAL_PORTS"/>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREERUN_FREQUENCY">125</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DIRECTION">BOTH</spirit:configurableElementValue>
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@ -649,10 +651,10 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDO_OUT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBTXUART_OUT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">33</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">13</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_USAGE_UPDATED">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PRESET">10GBASE-R</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_COMMA_PRESET_UPDATE">3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_COMMA_PRESET_UPDATE">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_USRCLK_FREQUENCY">156.2500000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TOTAL_NUM_CHANNELS">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TOTAL_NUM_COMMONS">2</spirit:configurableElementValue>
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@ -1352,7 +1354,8 @@
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<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.ubrsvdout_out">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.ubtxuart_out">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu3p</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvc1517</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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@ -1363,12 +1366,12 @@
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.2.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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<spirit:vendorExtensions>
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@ -1376,16 +1379,23 @@
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CHANNEL_ENABLE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FREERUN_FREQUENCY" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERNAL_PRESET" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRESET" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_CB_MAX_LEVEL" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_DATA_DECODING" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_INT_DATA_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_MASTER_CHANNEL" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_OUTCLK_SOURCE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_PPM_OFFSET" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_REFCLK_FREQUENCY" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_REFCLK_SOURCE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_USER_DATA_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SIM_CPLL_CAL_BYPASS" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TXPROGDIV_FREQ_VAL" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_DATA_ENCODING" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_INT_DATA_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_MASTER_CHANNEL" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_OUTCLK_SOURCE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_REFCLK_FREQUENCY" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_USER_DATA_WIDTH" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
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@ -1,127 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>xci</spirit:library>
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<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>ten_gig_eth_pcs_pma_0</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xxv_ethernet" spirit:version="2.2"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ANLT_CLK_IN_MHZ">75</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">7</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BASE_R_KR">BASE-R</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCKING">Asynchronous</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_INTERFACE">MII</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINE_REG">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_TIME_STAMPING">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_TX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY_CHK">virtexuplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAST_SIM_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_DRP_CLK">100.00</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_GROUP_SELECT">Quad X0Y0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_LOCATION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_REF_CLK_FREQ">156.25</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_TYPE">GTY</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_AUTO_NEG_LT_LOGIC">None</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_AXI4_INTERFACE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_FEC_LOGIC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_RSFEC_LOGIC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_USER_FIFO">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE1_GT_LOC">X0Y0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE2_GT_LOC">NA</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE3_GT_LOC">NA</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE4_GT_LOC">NA</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LINE_RATE">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_CORES">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PTP_CLOCKING_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PTP_OPERATION_MODE">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RUNTIME_SWITCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_LATENCY_ADJUST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_TOTAL_BYTES_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XGMII_INTERFACE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_BOARD_PROJECT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ANLT_CLK_IN_MHZ">100</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BASE_R_KR">BASE-R</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCKING">Asynchronous</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ten_gig_eth_pcs_pma_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE">MII</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFFCLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PIPELINE_REG">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TIME_STAMPING">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FAST_SIM_MODE">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DRP_CLK">100.00</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_GROUP_SELECT">Quad_X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_LOCATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_REF_CLK_FREQ">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_TYPE">GTY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_AUTO_NEG_LT_LOGIC">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_AXI4_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_FEC_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_RSFEC_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_USER_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE1_GT_LOC">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE2_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE3_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE4_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LINE_RATE">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_CORES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PTP_CLOCKING_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PTP_OPERATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUNTIME_SWITCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_LATENCY_ADJUST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XGMII_INTERFACE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu3p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvc1517</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.2.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BASE_R_KR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CORE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_TIME_STAMPING" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_LOCATION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_REF_CLK_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_SHARED_LOGIC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_USER_FIFO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LINE_RATE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@ -211,71 +211,71 @@ debounce_switch_inst (
|
||||
// XGMII 10G PHY
|
||||
assign qsfp_0_sel_l = 1'b0;
|
||||
|
||||
wire qsfp_0_tx_clk_0_int = clk_156mhz_int;
|
||||
wire qsfp_0_tx_rst_0_int = rst_156mhz_int;
|
||||
wire qsfp_0_tx_clk_0_int;
|
||||
wire qsfp_0_tx_rst_0_int;
|
||||
wire [63:0] qsfp_0_txd_0_int;
|
||||
wire [7:0] qsfp_0_txc_0_int;
|
||||
wire qsfp_0_rx_clk_0_int = clk_156mhz_int;
|
||||
wire qsfp_0_rx_rst_0_int = rst_156mhz_int;
|
||||
wire qsfp_0_rx_clk_0_int;
|
||||
wire qsfp_0_rx_rst_0_int;
|
||||
wire [63:0] qsfp_0_rxd_0_int;
|
||||
wire [7:0] qsfp_0_rxc_0_int;
|
||||
wire qsfp_0_tx_clk_1_int = clk_156mhz_int;
|
||||
wire qsfp_0_tx_rst_1_int = rst_156mhz_int;
|
||||
wire qsfp_0_tx_clk_1_int;
|
||||
wire qsfp_0_tx_rst_1_int;
|
||||
wire [63:0] qsfp_0_txd_1_int;
|
||||
wire [7:0] qsfp_0_txc_1_int;
|
||||
wire qsfp_0_rx_clk_1_int = clk_156mhz_int;
|
||||
wire qsfp_0_rx_rst_1_int = rst_156mhz_int;
|
||||
wire qsfp_0_rx_clk_1_int;
|
||||
wire qsfp_0_rx_rst_1_int;
|
||||
wire [63:0] qsfp_0_rxd_1_int;
|
||||
wire [7:0] qsfp_0_rxc_1_int;
|
||||
wire qsfp_0_tx_clk_2_int = clk_156mhz_int;
|
||||
wire qsfp_0_tx_rst_2_int = rst_156mhz_int;
|
||||
wire qsfp_0_tx_clk_2_int;
|
||||
wire qsfp_0_tx_rst_2_int;
|
||||
wire [63:0] qsfp_0_txd_2_int;
|
||||
wire [7:0] qsfp_0_txc_2_int;
|
||||
wire qsfp_0_rx_clk_2_int = clk_156mhz_int;
|
||||
wire qsfp_0_rx_rst_2_int = rst_156mhz_int;
|
||||
wire qsfp_0_rx_clk_2_int;
|
||||
wire qsfp_0_rx_rst_2_int;
|
||||
wire [63:0] qsfp_0_rxd_2_int;
|
||||
wire [7:0] qsfp_0_rxc_2_int;
|
||||
wire qsfp_0_tx_clk_3_int = clk_156mhz_int;
|
||||
wire qsfp_0_tx_rst_3_int = rst_156mhz_int;
|
||||
wire qsfp_0_tx_clk_3_int;
|
||||
wire qsfp_0_tx_rst_3_int;
|
||||
wire [63:0] qsfp_0_txd_3_int;
|
||||
wire [7:0] qsfp_0_txc_3_int;
|
||||
wire qsfp_0_rx_clk_3_int = clk_156mhz_int;
|
||||
wire qsfp_0_rx_rst_3_int = rst_156mhz_int;
|
||||
wire qsfp_0_rx_clk_3_int;
|
||||
wire qsfp_0_rx_rst_3_int;
|
||||
wire [63:0] qsfp_0_rxd_3_int;
|
||||
wire [7:0] qsfp_0_rxc_3_int;
|
||||
|
||||
assign qsfp_1_sel_l = 1'b0;
|
||||
|
||||
wire qsfp_1_tx_clk_0_int = clk_156mhz_int;
|
||||
wire qsfp_1_tx_rst_0_int = rst_156mhz_int;
|
||||
wire qsfp_1_tx_clk_0_int;
|
||||
wire qsfp_1_tx_rst_0_int;
|
||||
wire [63:0] qsfp_1_txd_0_int;
|
||||
wire [7:0] qsfp_1_txc_0_int;
|
||||
wire qsfp_1_rx_clk_0_int = clk_156mhz_int;
|
||||
wire qsfp_1_rx_rst_0_int = rst_156mhz_int;
|
||||
wire qsfp_1_rx_clk_0_int;
|
||||
wire qsfp_1_rx_rst_0_int;
|
||||
wire [63:0] qsfp_1_rxd_0_int;
|
||||
wire [7:0] qsfp_1_rxc_0_int;
|
||||
wire qsfp_1_tx_clk_1_int = clk_156mhz_int;
|
||||
wire qsfp_1_tx_rst_1_int = rst_156mhz_int;
|
||||
wire qsfp_1_tx_clk_1_int;
|
||||
wire qsfp_1_tx_rst_1_int;
|
||||
wire [63:0] qsfp_1_txd_1_int;
|
||||
wire [7:0] qsfp_1_txc_1_int;
|
||||
wire qsfp_1_rx_clk_1_int = clk_156mhz_int;
|
||||
wire qsfp_1_rx_rst_1_int = rst_156mhz_int;
|
||||
wire qsfp_1_rx_clk_1_int;
|
||||
wire qsfp_1_rx_rst_1_int;
|
||||
wire [63:0] qsfp_1_rxd_1_int;
|
||||
wire [7:0] qsfp_1_rxc_1_int;
|
||||
wire qsfp_1_tx_clk_2_int = clk_156mhz_int;
|
||||
wire qsfp_1_tx_rst_2_int = rst_156mhz_int;
|
||||
wire qsfp_1_tx_clk_2_int;
|
||||
wire qsfp_1_tx_rst_2_int;
|
||||
wire [63:0] qsfp_1_txd_2_int;
|
||||
wire [7:0] qsfp_1_txc_2_int;
|
||||
wire qsfp_1_rx_clk_2_int = clk_156mhz_int;
|
||||
wire qsfp_1_rx_rst_2_int = rst_156mhz_int;
|
||||
wire qsfp_1_rx_clk_2_int;
|
||||
wire qsfp_1_rx_rst_2_int;
|
||||
wire [63:0] qsfp_1_rxd_2_int;
|
||||
wire [7:0] qsfp_1_rxc_2_int;
|
||||
wire qsfp_1_tx_clk_3_int = clk_156mhz_int;
|
||||
wire qsfp_1_tx_rst_3_int = rst_156mhz_int;
|
||||
wire qsfp_1_tx_clk_3_int;
|
||||
wire qsfp_1_tx_rst_3_int;
|
||||
wire [63:0] qsfp_1_txd_3_int;
|
||||
wire [7:0] qsfp_1_txc_3_int;
|
||||
wire qsfp_1_rx_clk_3_int = clk_156mhz_int;
|
||||
wire qsfp_1_rx_rst_3_int = rst_156mhz_int;
|
||||
wire qsfp_1_rx_clk_3_int;
|
||||
wire qsfp_1_rx_rst_3_int;
|
||||
wire [63:0] qsfp_1_rxd_3_int;
|
||||
wire [7:0] qsfp_1_rxc_3_int;
|
||||
|
||||
@ -509,508 +509,284 @@ qsfp_gty_inst (
|
||||
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
||||
);
|
||||
|
||||
wire qsfp_0_serdes_reset_0;
|
||||
assign qsfp_0_tx_clk_0_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_0_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_0_int = gt_rxusrclk[4];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_pcs_pma_0_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[0]),
|
||||
qsfp_0_rx_rst_0_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_0_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_serdes_reset_0)
|
||||
.sync_reset_out(qsfp_0_rx_rst_0_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_0_pcs_pma_0 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_0_rxd_0_int),
|
||||
.rx_mii_c_0(qsfp_0_rxc_0_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_0_rx_block_lock_0),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_0_txd_0_int),
|
||||
.tx_mii_c_0(qsfp_0_txc_0_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[4]),
|
||||
.rx_serdes_reset_0(qsfp_0_serdes_reset_0),
|
||||
.rxgearboxslip_in_0(qsfp_0_gt_rxgearboxslip_0),
|
||||
.rxdatavalid_out_0(qsfp_0_gt_rxdatavalid_0),
|
||||
.rxheader_out_0(qsfp_0_gt_rxheader_0),
|
||||
.rxheadervalid_out_0(qsfp_0_gt_rxheadervalid_0),
|
||||
.rx_serdes_data_out_0(qsfp_0_gt_rxdata_0),
|
||||
.tx_serdes_data_in_0(qsfp_0_gt_txdata_0),
|
||||
.txheader_in_0(qsfp_0_gt_txheader_0)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_0_phy_0_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_0_int),
|
||||
.tx_rst(qsfp_0_tx_rst_0_int),
|
||||
.rx_clk(qsfp_0_rx_clk_0_int),
|
||||
.rx_rst(qsfp_0_rx_rst_0_int),
|
||||
.xgmii_txd(qsfp_0_txd_0_int),
|
||||
.xgmii_txc(qsfp_0_txc_0_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_0_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_0_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_0),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_0),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_0),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_0),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_0),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_0),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_0_serdes_reset_1;
|
||||
assign qsfp_0_tx_clk_1_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_1_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_1_int = gt_rxusrclk[5];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_pcs_pma_1_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[1]),
|
||||
qsfp_0_rx_rst_1_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_1_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_serdes_reset_1)
|
||||
.sync_reset_out(qsfp_0_rx_rst_1_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_0_pcs_pma_1 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_0_rxd_1_int),
|
||||
.rx_mii_c_0(qsfp_0_rxc_1_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_0_rx_block_lock_1),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_0_txd_1_int),
|
||||
.tx_mii_c_0(qsfp_0_txc_1_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[5]),
|
||||
.rx_serdes_reset_0(qsfp_0_serdes_reset_1),
|
||||
.rxgearboxslip_in_0(qsfp_0_gt_rxgearboxslip_1),
|
||||
.rxdatavalid_out_0(qsfp_0_gt_rxdatavalid_1),
|
||||
.rxheader_out_0(qsfp_0_gt_rxheader_1),
|
||||
.rxheadervalid_out_0(qsfp_0_gt_rxheadervalid_1),
|
||||
.rx_serdes_data_out_0(qsfp_0_gt_rxdata_1),
|
||||
.tx_serdes_data_in_0(qsfp_0_gt_txdata_1),
|
||||
.txheader_in_0(qsfp_0_gt_txheader_1)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_0_phy_1_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_1_int),
|
||||
.tx_rst(qsfp_0_tx_rst_1_int),
|
||||
.rx_clk(qsfp_0_rx_clk_1_int),
|
||||
.rx_rst(qsfp_0_rx_rst_1_int),
|
||||
.xgmii_txd(qsfp_0_txd_1_int),
|
||||
.xgmii_txc(qsfp_0_txc_1_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_1_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_1_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_1),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_1),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_1),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_1),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_1),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_1),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_0_serdes_reset_2;
|
||||
assign qsfp_0_tx_clk_2_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_2_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_2_int = gt_rxusrclk[6];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_pcs_pma_2_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[2]),
|
||||
qsfp_0_rx_rst_2_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_2_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_serdes_reset_2)
|
||||
.sync_reset_out(qsfp_0_rx_rst_2_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_0_pcs_pma_2 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_0_rxd_2_int),
|
||||
.rx_mii_c_0(qsfp_0_rxc_2_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_0_rx_block_lock_2),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_0_txd_2_int),
|
||||
.tx_mii_c_0(qsfp_0_txc_2_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[6]),
|
||||
.rx_serdes_reset_0(qsfp_0_serdes_reset_2),
|
||||
.rxgearboxslip_in_0(qsfp_0_gt_rxgearboxslip_2),
|
||||
.rxdatavalid_out_0(qsfp_0_gt_rxdatavalid_2),
|
||||
.rxheader_out_0(qsfp_0_gt_rxheader_2),
|
||||
.rxheadervalid_out_0(qsfp_0_gt_rxheadervalid_2),
|
||||
.rx_serdes_data_out_0(qsfp_0_gt_rxdata_2),
|
||||
.tx_serdes_data_in_0(qsfp_0_gt_txdata_2),
|
||||
.txheader_in_0(qsfp_0_gt_txheader_2)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_0_phy_2_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_2_int),
|
||||
.tx_rst(qsfp_0_tx_rst_2_int),
|
||||
.rx_clk(qsfp_0_rx_clk_2_int),
|
||||
.rx_rst(qsfp_0_rx_rst_2_int),
|
||||
.xgmii_txd(qsfp_0_txd_2_int),
|
||||
.xgmii_txc(qsfp_0_txc_2_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_2_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_2_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_2),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_2),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_2),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_2),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_2),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_2),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_0_serdes_reset_3;
|
||||
assign qsfp_0_tx_clk_3_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_3_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_3_int = gt_rxusrclk[7];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_pcs_pma_3_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[3]),
|
||||
qsfp_0_rx_rst_3_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_3_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_serdes_reset_3)
|
||||
.sync_reset_out(qsfp_0_rx_rst_3_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_0_pcs_pma_3 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_0_rxd_3_int),
|
||||
.rx_mii_c_0(qsfp_0_rxc_3_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_0_rx_block_lock_3),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_0_txd_3_int),
|
||||
.tx_mii_c_0(qsfp_0_txc_3_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[7]),
|
||||
.rx_serdes_reset_0(qsfp_0_serdes_reset_3),
|
||||
.rxgearboxslip_in_0(qsfp_0_gt_rxgearboxslip_3),
|
||||
.rxdatavalid_out_0(qsfp_0_gt_rxdatavalid_3),
|
||||
.rxheader_out_0(qsfp_0_gt_rxheader_3),
|
||||
.rxheadervalid_out_0(qsfp_0_gt_rxheadervalid_3),
|
||||
.rx_serdes_data_out_0(qsfp_0_gt_rxdata_3),
|
||||
.tx_serdes_data_in_0(qsfp_0_gt_txdata_3),
|
||||
.txheader_in_0(qsfp_0_gt_txheader_3)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_0_phy_3_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_3_int),
|
||||
.tx_rst(qsfp_0_tx_rst_3_int),
|
||||
.rx_clk(qsfp_0_rx_clk_3_int),
|
||||
.rx_rst(qsfp_0_rx_rst_3_int),
|
||||
.xgmii_txd(qsfp_0_txd_3_int),
|
||||
.xgmii_txc(qsfp_0_txc_3_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_3_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_3_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_3),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_3),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_3),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_3),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_3),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_3),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_1_serdes_reset_0;
|
||||
assign qsfp_1_tx_clk_0_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_0_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_0_int = gt_rxusrclk[0];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_pcs_pma_0_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[4]),
|
||||
qsfp_1_rx_rst_0_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_0_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_serdes_reset_0)
|
||||
.sync_reset_out(qsfp_1_rx_rst_0_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_1_pcs_pma_0 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_1_rxd_0_int),
|
||||
.rx_mii_c_0(qsfp_1_rxc_0_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_1_rx_block_lock_0),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_1_txd_0_int),
|
||||
.tx_mii_c_0(qsfp_1_txc_0_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[0]),
|
||||
.rx_serdes_reset_0(qsfp_1_serdes_reset_0),
|
||||
.rxgearboxslip_in_0(qsfp_1_gt_rxgearboxslip_0),
|
||||
.rxdatavalid_out_0(qsfp_1_gt_rxdatavalid_0),
|
||||
.rxheader_out_0(qsfp_1_gt_rxheader_0),
|
||||
.rxheadervalid_out_0(qsfp_1_gt_rxheadervalid_0),
|
||||
.rx_serdes_data_out_0(qsfp_1_gt_rxdata_0),
|
||||
.tx_serdes_data_in_0(qsfp_1_gt_txdata_0),
|
||||
.txheader_in_0(qsfp_1_gt_txheader_0)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_1_phy_0_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_0_int),
|
||||
.tx_rst(qsfp_1_tx_rst_0_int),
|
||||
.rx_clk(qsfp_1_rx_clk_0_int),
|
||||
.rx_rst(qsfp_1_rx_rst_0_int),
|
||||
.xgmii_txd(qsfp_1_txd_0_int),
|
||||
.xgmii_txc(qsfp_1_txc_0_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_0_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_0_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_0),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_0),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_0),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_0),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_0),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_0),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_1_serdes_reset_1;
|
||||
assign qsfp_1_tx_clk_1_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_1_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_1_int = gt_rxusrclk[1];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_pcs_pma_1_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[5]),
|
||||
qsfp_1_rx_rst_1_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_1_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_serdes_reset_1)
|
||||
.sync_reset_out(qsfp_1_rx_rst_1_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_1_pcs_pma_1 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_1_rxd_1_int),
|
||||
.rx_mii_c_0(qsfp_1_rxc_1_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_1_rx_block_lock_1),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_1_txd_1_int),
|
||||
.tx_mii_c_0(qsfp_1_txc_1_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[1]),
|
||||
.rx_serdes_reset_0(qsfp_1_serdes_reset_1),
|
||||
.rxgearboxslip_in_0(qsfp_1_gt_rxgearboxslip_1),
|
||||
.rxdatavalid_out_0(qsfp_1_gt_rxdatavalid_1),
|
||||
.rxheader_out_0(qsfp_1_gt_rxheader_1),
|
||||
.rxheadervalid_out_0(qsfp_1_gt_rxheadervalid_1),
|
||||
.rx_serdes_data_out_0(qsfp_1_gt_rxdata_1),
|
||||
.tx_serdes_data_in_0(qsfp_1_gt_txdata_1),
|
||||
.txheader_in_0(qsfp_1_gt_txheader_1)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_1_phy_1_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_1_int),
|
||||
.tx_rst(qsfp_1_tx_rst_1_int),
|
||||
.rx_clk(qsfp_1_rx_clk_1_int),
|
||||
.rx_rst(qsfp_1_rx_rst_1_int),
|
||||
.xgmii_txd(qsfp_1_txd_1_int),
|
||||
.xgmii_txc(qsfp_1_txc_1_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_1_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_1_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_1),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_1),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_1),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_1),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_1),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_1),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_1_serdes_reset_2;
|
||||
assign qsfp_1_tx_clk_2_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_2_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_2_int = gt_rxusrclk[2];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_pcs_pma_2_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[6]),
|
||||
qsfp_1_rx_rst_2_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_2_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_serdes_reset_2)
|
||||
.sync_reset_out(qsfp_1_rx_rst_2_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_1_pcs_pma_2 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_1_rxd_2_int),
|
||||
.rx_mii_c_0(qsfp_1_rxc_2_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_1_rx_block_lock_2),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_1_txd_2_int),
|
||||
.tx_mii_c_0(qsfp_1_txc_2_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[2]),
|
||||
.rx_serdes_reset_0(qsfp_1_serdes_reset_2),
|
||||
.rxgearboxslip_in_0(qsfp_1_gt_rxgearboxslip_2),
|
||||
.rxdatavalid_out_0(qsfp_1_gt_rxdatavalid_2),
|
||||
.rxheader_out_0(qsfp_1_gt_rxheader_2),
|
||||
.rxheadervalid_out_0(qsfp_1_gt_rxheadervalid_2),
|
||||
.rx_serdes_data_out_0(qsfp_1_gt_rxdata_2),
|
||||
.tx_serdes_data_in_0(qsfp_1_gt_txdata_2),
|
||||
.txheader_in_0(qsfp_1_gt_txheader_2)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_1_phy_2_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_2_int),
|
||||
.tx_rst(qsfp_1_tx_rst_2_int),
|
||||
.rx_clk(qsfp_1_rx_clk_2_int),
|
||||
.rx_rst(qsfp_1_rx_rst_2_int),
|
||||
.xgmii_txd(qsfp_1_txd_2_int),
|
||||
.xgmii_txc(qsfp_1_txc_2_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_2_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_2_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_2),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_2),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_2),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_2),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_2),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_2),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
wire qsfp_1_serdes_reset_3;
|
||||
assign qsfp_1_tx_clk_3_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_3_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_3_int = gt_rxusrclk[3];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_pcs_pma_3_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[7]),
|
||||
qsfp_1_rx_rst_3_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_3_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_serdes_reset_3)
|
||||
.sync_reset_out(qsfp_1_rx_rst_3_int)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
qsfp_1_pcs_pma_3 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(qsfp_1_rxd_3_int),
|
||||
.rx_mii_c_0(qsfp_1_rxc_3_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(qsfp_1_rx_block_lock_3),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(qsfp_1_txd_3_int),
|
||||
.tx_mii_c_0(qsfp_1_txc_3_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTY interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk[3]),
|
||||
.rx_serdes_reset_0(qsfp_1_serdes_reset_3),
|
||||
.rxgearboxslip_in_0(qsfp_1_gt_rxgearboxslip_3),
|
||||
.rxdatavalid_out_0(qsfp_1_gt_rxdatavalid_3),
|
||||
.rxheader_out_0(qsfp_1_gt_rxheader_3),
|
||||
.rxheadervalid_out_0(qsfp_1_gt_rxheadervalid_3),
|
||||
.rx_serdes_data_out_0(qsfp_1_gt_rxdata_3),
|
||||
.tx_serdes_data_in_0(qsfp_1_gt_txdata_3),
|
||||
.txheader_in_0(qsfp_1_gt_txheader_3)
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
qsfp_1_phy_3_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_3_int),
|
||||
.tx_rst(qsfp_1_tx_rst_3_int),
|
||||
.rx_clk(qsfp_1_rx_clk_3_int),
|
||||
.rx_rst(qsfp_1_rx_rst_3_int),
|
||||
.xgmii_txd(qsfp_1_txd_3_int),
|
||||
.xgmii_txc(qsfp_1_txc_3_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_3_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_3_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_3),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_3),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_3),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_3),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_3),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_3),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
//assign led = sw[0] ? {qsfp_1_rx_block_lock_4, qsfp_1_rx_block_lock_3, qsfp_1_rx_block_lock_2, qsfp_1_rx_block_lock_1, qsfp_0_rx_block_lock_4, qsfp_0_rx_block_lock_3, qsfp_0_rx_block_lock_2, qsfp_0_rx_block_lock_1} : led_int;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user