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Update example design timing constraints

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This commit is contained in:
Alex Forencich 2019-03-28 17:59:30 -07:00
parent e120a85607
commit 0ca8c9a59b
16 changed files with 18 additions and 48 deletions
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5
example/ADM_PCIE_9V3/fpga_10g/fpga.xdc
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@ -16,7 +16,6 @@ set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
set_clock_groups -asynchronous -group [get_clocks clk_300mhz -include_generated_clocks]
# LEDs
set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
@ -59,7 +58,6 @@ set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
# 161.1328125 MHz MGT reference clock
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
set_clock_groups -asynchronous -group [get_clocks qsfp_0_mgt_refclk -include_generated_clocks]
set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
#set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
@ -84,7 +82,6 @@ set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
# 161.1328125 MHz MGT reference clock
create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
set_clock_groups -asynchronous -group [get_clocks qsfp_1_mgt_refclk -include_generated_clocks]
set_property -dict {LOC B29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_reset_l]
set_property -dict {LOC C29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_int_l]
@ -165,9 +162,7 @@ set_property -dict {LOC C29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
# 100 MHz MGT reference clock
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
#set_clock_groups -asynchronous -group [get_clocks pcie_mgt_refclk_1 -include_generated_clocks]
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
#set_clock_groups -asynchronous -group [get_clocks pcie_mgt_refclk_2 -include_generated_clocks]
# QSPI flash
#set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_clk}]

2
example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
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@ -46,6 +46,8 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
# IP
XCI_FILES += ip/gtwizard_ultrascale_0.xci

3
example/ExaNIC_X10/fpga/fpga.xdc
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@ -14,7 +14,6 @@ set_property CONFIG_MODE BPI16 [current_design]
set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p]
set_property -dict {LOC C18 IOSTANDARD LVDS} [get_ports clk_100mhz_n]
create_clock -period 10 -name clk_100mhz [get_ports clk_100mhz_p]
set_clock_groups -asynchronous -group [get_clocks clk_100mhz -include_generated_clocks]
# LEDs
set_property -dict {LOC A25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
@ -61,7 +60,6 @@ set_property -dict {LOC D25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
# 161.1328125 MHz MGT reference clock
create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
set_clock_groups -asynchronous -group [get_clocks sfp_mgt_refclk -include_generated_clocks]
# I2C interface
#set_property -dict {LOC B26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
@ -106,7 +104,6 @@ set_clock_groups -asynchronous -group [get_clocks sfp_mgt_refclk -include_genera
# 100 MHz MGT reference clock
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
#set_clock_groups -asynchronous -group [get_clocks pcie_mgt_refclk -include_generated_clocks]
# Flash
#set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[0]}]

2
example/ExaNIC_X10/fpga/fpga/Makefile
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@ -45,6 +45,8 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
# IP
XCI_FILES = ip/gtwizard_ultrascale_0.xci

2
example/NexysVideo/fpga/fpga.xdc
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@ -9,7 +9,6 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
# 100 MHz clock
set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]
create_clock -period 10.000 -name clk [get_ports clk]
set_clock_groups -asynchronous -group [get_clocks clk -include_generated_clocks]
# LEDs
set_property -dict {LOC T14 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
@ -65,5 +64,4 @@ set_property -dict {LOC W14 IOSTANDARD LVCMOS25} [get_ports phy_pme_n]
#set_property -dict {LOC AA16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
set_clock_groups -asynchronous -group [get_clocks phy_rx_clk -include_generated_clocks]

4
example/NexysVideo/fpga/fpga/Makefile
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@ -46,6 +46,10 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/rgmii_phy_if.tcl
XDC_FILES += lib/eth/syn/eth_mac_1g_rgmii.tcl
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
include ../common/vivado.mk

4
example/VCU108/fpga_10g/clock.xdc
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@ -1,4 +0,0 @@
# Clock constraints
# internal clock groups
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_nets clk_156mhz_int]]

5
example/VCU108/fpga_10g/fpga.xdc
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@ -11,23 +11,19 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks]
#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_2 -include_generated_clocks]
# 125 MHz
set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks]
# 90 MHz
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
@ -75,7 +71,6 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
# 625 MHz ref clock from SGMII PHY
create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]
# QSFP+ Interface
set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3

3
example/VCU108/fpga_10g/fpga/Makefile
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@ -48,8 +48,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += clock.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

5
example/VCU108/fpga_1g/fpga.xdc
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@ -11,23 +11,19 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks]
#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_2 -include_generated_clocks]
# 125 MHz
set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks]
# 90 MHz
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
@ -75,5 +71,4 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
# 625 MHz ref clock from SGMII PHY
create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]

2
example/VCU108/fpga_1g/fpga/Makefile
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@ -40,6 +40,8 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += eth.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

4
example/VCU118/fpga_10g/clock.xdc
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@ -1,4 +0,0 @@
# Clock constraints
# internal clock groups
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_nets clk_156mhz_int]]

10
example/VCU118/fpga_10g/fpga.xdc
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@ -11,29 +11,24 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz -include_generated_clocks]
# 250 MHz
#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p]
#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n]
#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p]
#set_clock_groups -asynchronous -group [get_clocks clk_250mhz_1 -include_generated_clocks]
#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p]
#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n]
#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p]
#set_clock_groups -asynchronous -group [get_clocks clk_250mhz_2 -include_generated_clocks]
# 125 MHz
set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks]
# 90 MHz
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
@ -80,8 +75,7 @@ set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports p
set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
# 625 MHz ref clock from SGMII PHY
create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]
#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
# QSFP28 Interfaces
set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXN0_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12
@ -114,7 +108,6 @@ set_property -dict {LOC AN21 IOSTANDARD LVCMOS18} [get_ports qsfp1_lpmode]
# 156.25 MHz MGT reference clock
create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
set_clock_groups -asynchronous -group [get_clocks qsfp1_mgt_refclk_0 -include_generated_clocks]
set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXN0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13
#set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXP0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13
@ -146,7 +139,6 @@ set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp2_lpmode]
# 156.25 MHz MGT reference clock
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
#set_clock_groups -asynchronous -group [get_clocks qsfp2_mgt_refclk_0 -include_generated_clocks]
# I2C interface
set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

3
example/VCU118/fpga_10g/fpga/Makefile
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@ -54,7 +54,8 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += clock.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci

10
example/VCU118/fpga_1g/fpga.xdc
View File

@ -11,29 +11,24 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz -include_generated_clocks]
# 250 MHz
#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p]
#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n]
#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p]
#set_clock_groups -asynchronous -group [get_clocks clk_250mhz_1 -include_generated_clocks]
#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p]
#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n]
#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p]
#set_clock_groups -asynchronous -group [get_clocks clk_250mhz_2 -include_generated_clocks]
# 125 MHz
set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks]
# 90 MHz
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
@ -80,8 +75,7 @@ set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports p
set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
# 625 MHz ref clock from SGMII PHY
create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]
#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
# QSFP28 Interfaces
#set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXN0_231 GTYE3_CHANNEL_X1Y48 / GTYE3_COMMON_X1Y12
@ -114,7 +108,6 @@ set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generat
# 156.25 MHz MGT reference clock
#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
#set_clock_groups -asynchronous -group [get_clocks qsfp1_mgt_refclk_0 -include_generated_clocks]
#set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXN0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13
#set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXP0_232 GTYE3_CHANNEL_X1Y52 / GTYE3_COMMON_X1Y13
@ -146,7 +139,6 @@ set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generat
# 156.25 MHz MGT reference clock
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
#set_clock_groups -asynchronous -group [get_clocks qsfp2_mgt_refclk_0 -include_generated_clocks]
# I2C interface
#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

2
example/VCU118/fpga_1g/fpga/Makefile
View File

@ -40,6 +40,8 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
# IP
XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci