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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap

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Alex Forencich 2017-11-20 23:45:34 -08:00
parent 4ef4ef2622
commit 0edafd58ac
6 changed files with 433 additions and 413 deletions
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127
rtl/axis_tap.v
View File

@ -31,7 +31,17 @@ THE SOFTWARE.
*/
module axis_tap #
(
parameter DATA_WIDTH = 8
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter USER_BAD_FRAME_VALUE = 1'b1,
parameter USER_BAD_FRAME_MASK = 1'b1
)
(
input wire clk,
@ -41,28 +51,44 @@ module axis_tap #
* AXI tap
*/
input wire [DATA_WIDTH-1:0] tap_axis_tdata,
input wire [KEEP_WIDTH-1:0] tap_axis_tkeep,
input wire tap_axis_tvalid,
input wire tap_axis_tready,
input wire tap_axis_tlast,
input wire tap_axis_tuser,
input wire [ID_WIDTH-1:0] tap_axis_tid,
input wire [DEST_WIDTH-1:0] tap_axis_tdest,
input wire [USER_WIDTH-1:0] tap_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
);
// datapath control signals
reg store_last_word;
reg [ID_WIDTH-1:0] last_word_id_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] last_word_dest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] last_word_user_reg = {USER_WIDTH{1'b0}};
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
localparam [1:0]
STATE_IDLE = 2'd0,
@ -77,12 +103,17 @@ reg frame_reg = 1'b0, frame_next;
always @* begin
state_next = STATE_IDLE;
store_last_word = 1'b0;
frame_next = frame_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tid_int = {ID_WIDTH{1'b0}};
output_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_axis_tuser_int = {USER_WIDTH{1'b0}};
if (tap_axis_tready & tap_axis_tvalid) begin
frame_next = ~tap_axis_tlast;
@ -93,10 +124,13 @@ always @* begin
if (tap_axis_tready & tap_axis_tvalid) begin
// start of frame
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata;
output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tid_int = tap_axis_tid;
output_axis_tdest_int = tap_axis_tdest;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
@ -113,16 +147,20 @@ always @* begin
if (tap_axis_tready & tap_axis_tvalid) begin
// transfer data
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata;
output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tid_int = tap_axis_tid;
output_axis_tdest_int = tap_axis_tdest;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRANSFER;
end
end else begin
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
@ -131,10 +169,13 @@ always @* begin
end
STATE_TRUNCATE: begin
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {{KEEP_WIDTH-1{1'b0}}, 1'b1};
output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = 1'b1;
output_axis_tlast_int = 1'b1;
output_axis_tid_int = last_word_id_reg;
output_axis_tdest_int = last_word_dest_reg;
output_axis_tuser_int = (last_word_user_reg & ~USER_BAD_FRAME_MASK) | (USER_BAD_FRAME_VALUE & USER_BAD_FRAME_MASK);
if (frame_next) begin
state_next = STATE_WAIT;
end else begin
@ -166,28 +207,43 @@ always @(posedge clk) begin
state_reg <= state_next;
frame_reg <= frame_next;
end
if (store_last_word) begin
last_word_id_reg <= tap_axis_tid;
last_word_dest_reg <= tap_axis_tdest;
last_word_user_reg <= tap_axis_tuser;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg output_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
reg temp_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -200,7 +256,7 @@ always @* begin
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -234,17 +290,26 @@ always @(posedge clk) begin
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end

266
rtl/axis_tap_64.v
View File

@ -1,266 +0,0 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream tap (64 bit datapath)
*/
module axis_tap_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI tap
*/
input wire [DATA_WIDTH-1:0] tap_axis_tdata,
input wire [KEEP_WIDTH-1:0] tap_axis_tkeep,
input wire tap_axis_tvalid,
input wire tap_axis_tready,
input wire tap_axis_tlast,
input wire tap_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_TRANSFER = 2'd1,
STATE_TRUNCATE = 2'd2,
STATE_WAIT = 2'd3;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg frame_reg = 1'b0, frame_next;
always @* begin
state_next = STATE_IDLE;
frame_next = frame_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
if (tap_axis_tready & tap_axis_tvalid) begin
frame_next = ~tap_axis_tlast;
end
case (state_reg)
STATE_IDLE: begin
if (tap_axis_tready & tap_axis_tvalid) begin
// start of frame
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WAIT;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_TRANSFER: begin
if (tap_axis_tready & tap_axis_tvalid) begin
// transfer data
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_TRUNCATE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_TRUNCATE: begin
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {{KEEP_WIDTH-1{1'b0}}, 1'b1};
output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = 1'b1;
if (frame_next) begin
state_next = STATE_WAIT;
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRUNCATE;
end
end
STATE_WAIT: begin
if (tap_axis_tready & tap_axis_tvalid) begin
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT;
end
end else begin
state_next = STATE_WAIT;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_reg <= frame_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule

182
tb/test_axis_tap.py
View File

@ -44,6 +44,16 @@ def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
# Inputs
clk = Signal(bool(0))
@ -51,17 +61,23 @@ def bench():
current_test = Signal(intbv(0)[8:])
tap_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
tap_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
tap_axis_tvalid = Signal(bool(0))
tap_axis_tready = Signal(bool(1))
tap_axis_tlast = Signal(bool(0))
tap_axis_tuser = Signal(bool(0))
tap_axis_tid = Signal(intbv(0)[ID_WIDTH:])
tap_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
tap_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause = Signal(bool(0))
@ -73,9 +89,12 @@ def bench():
clk,
rst,
tdata=tap_axis_tdata,
tkeep=tap_axis_tkeep,
tvalid=tap_axis_tvalid,
tready=tap_axis_tready,
tlast=tap_axis_tlast,
tid=tap_axis_tid,
tdest=tap_axis_tdest,
tuser=tap_axis_tuser,
pause=source_pause,
name='source'
@ -87,9 +106,12 @@ def bench():
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
@ -106,15 +128,21 @@ def bench():
current_test=current_test,
tap_axis_tdata=tap_axis_tdata,
tap_axis_tkeep=tap_axis_tkeep,
tap_axis_tvalid=tap_axis_tvalid,
tap_axis_tready=tap_axis_tready,
tap_axis_tlast=tap_axis_tlast,
tap_axis_tid=tap_axis_tid,
tap_axis_tdest=tap_axis_tdest,
tap_axis_tuser=tap_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser
)
@ -139,10 +167,15 @@ def bench():
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -160,10 +193,15 @@ def bench():
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -181,10 +219,15 @@ def bench():
print("test 3: test packet with source pause")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -209,10 +252,15 @@ def bench():
print("test 4: test packet with sink pause")
current_test.next = 4
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -229,7 +277,7 @@ def bench():
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
yield delay(100)
@ -237,14 +285,23 @@ def bench():
print("test 5: back-to-back packets")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
@ -269,14 +326,23 @@ def bench():
print("test 6: alternate pause source")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
@ -306,14 +372,23 @@ def bench():
print("test 7: alternate pause sink")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
@ -331,11 +406,11 @@ def bench():
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
yield delay(100)
@ -343,11 +418,16 @@ def bench():
print("test 8: tuser assert")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=8,
dest=1,
last_cycle_user=1
)
source.send(test_frame)
yield clk.posedge
@ -358,7 +438,7 @@ def bench():
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
yield delay(100)

44
tb/test_axis_tap.v
View File

@ -33,6 +33,16 @@ module test_axis_tap;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
// Inputs
reg clk = 0;
@ -40,17 +50,23 @@ reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
reg tap_axis_tuser = 0;
reg [ID_WIDTH-1:0] tap_axis_tid = 0;
reg [DEST_WIDTH-1:0] tap_axis_tdest = 0;
reg [USER_WIDTH-1:0] tap_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin
// myhdl integration
@ -59,16 +75,22 @@ initial begin
rst,
current_test,
tap_axis_tdata,
tap_axis_tkeep,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tid,
tap_axis_tdest,
tap_axis_tuser,
output_axis_tready
);
$to_myhdl(
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser
);
@ -78,22 +100,38 @@ initial begin
end
axis_tap #(
.DATA_WIDTH(DATA_WIDTH)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK)
)
UUT (
.clk(clk),
.rst(rst),
// AXI tap
.tap_axis_tdata(tap_axis_tdata),
.tap_axis_tkeep(tap_axis_tkeep),
.tap_axis_tvalid(tap_axis_tvalid),
.tap_axis_tready(tap_axis_tready),
.tap_axis_tlast(tap_axis_tlast),
.tap_axis_tid(tap_axis_tid),
.tap_axis_tdest(tap_axis_tdest),
.tap_axis_tuser(tap_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser)
);

183
tb/test_axis_tap_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep
module = 'axis_tap_64'
testbench = 'test_%s' % module
module = 'axis_tap'
testbench = 'test_%s_64' % module
srcs = []
@ -44,7 +44,16 @@ def bench():
# Parameters
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
# Inputs
clk = Signal(bool(0))
@ -52,19 +61,23 @@ def bench():
current_test = Signal(intbv(0)[8:])
tap_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
tap_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
tap_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
tap_axis_tvalid = Signal(bool(0))
tap_axis_tready = Signal(bool(1))
tap_axis_tlast = Signal(bool(0))
tap_axis_tuser = Signal(bool(0))
tap_axis_tid = Signal(intbv(0)[ID_WIDTH:])
tap_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
tap_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause = Signal(bool(0))
@ -80,6 +93,8 @@ def bench():
tvalid=tap_axis_tvalid,
tready=tap_axis_tready,
tlast=tap_axis_tlast,
tid=tap_axis_tid,
tdest=tap_axis_tdest,
tuser=tap_axis_tuser,
pause=source_pause,
name='source'
@ -95,6 +110,8 @@ def bench():
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
@ -115,6 +132,8 @@ def bench():
tap_axis_tvalid=tap_axis_tvalid,
tap_axis_tready=tap_axis_tready,
tap_axis_tlast=tap_axis_tlast,
tap_axis_tid=tap_axis_tid,
tap_axis_tdest=tap_axis_tdest,
tap_axis_tuser=tap_axis_tuser,
output_axis_tdata=output_axis_tdata,
@ -122,6 +141,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser
)
@ -146,10 +167,15 @@ def bench():
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -167,10 +193,15 @@ def bench():
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -188,10 +219,15 @@ def bench():
print("test 3: test packet with source pause")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -216,10 +252,15 @@ def bench():
print("test 4: test packet with sink pause")
current_test.next = 4
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=4,
dest=1
)
source.send(test_frame)
yield clk.posedge
@ -236,7 +277,7 @@ def bench():
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
yield delay(100)
@ -244,14 +285,23 @@ def bench():
print("test 5: back-to-back packets")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
@ -276,14 +326,23 @@ def bench():
print("test 6: alternate pause source")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
@ -313,14 +372,23 @@ def bench():
print("test 7: alternate pause sink")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=7,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=7,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
@ -338,11 +406,11 @@ def bench():
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
yield delay(100)
@ -350,11 +418,16 @@ def bench():
print("test 8: tuser assert")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=8,
dest=1,
last_cycle_user=1
)
source.send(test_frame)
yield clk.posedge
@ -365,7 +438,7 @@ def bench():
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
yield delay(100)

44
tb/test_axis_tap_64.v
View File

@ -27,13 +27,22 @@ THE SOFTWARE.
`timescale 1ns / 1ps
/*
* Testbench for axis_tap_64
* Testbench for axis_tap
*/
module test_axis_tap_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
// Inputs
reg clk = 0;
@ -41,19 +50,23 @@ reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg [DATA_WIDTH-1:0] tap_axis_tkeep = 0;
reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
reg tap_axis_tuser = 0;
reg [ID_WIDTH-1:0] tap_axis_tid = 0;
reg [DEST_WIDTH-1:0] tap_axis_tdest = 0;
reg [USER_WIDTH-1:0] tap_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [DATA_WIDTH-1:0] output_axis_tkeep;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin
// myhdl integration
@ -66,6 +79,8 @@ initial begin
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tid,
tap_axis_tdest,
tap_axis_tuser,
output_axis_tready
);
@ -74,6 +89,8 @@ initial begin
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser
);
@ -82,9 +99,18 @@ initial begin
$dumpvars(0, test_axis_tap_64);
end
axis_tap_64 #(
axis_tap #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK)
)
UUT (
.clk(clk),
@ -95,6 +121,8 @@ UUT (
.tap_axis_tvalid(tap_axis_tvalid),
.tap_axis_tready(tap_axis_tready),
.tap_axis_tlast(tap_axis_tlast),
.tap_axis_tid(tap_axis_tid),
.tap_axis_tdest(tap_axis_tdest),
.tap_axis_tuser(tap_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
@ -102,6 +130,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser)
);