Fix wires

example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v

@@ -356,8 +356,6 @@ assign user_led_g = ~led_reg[1:0];
 assign user_led_r = 1'b1;
 assign front_led = 2'b00;
 
-assign phy_reset_n = !rst;
-
 assign qsfp_0_txd_1 = 64'h0707070707070707;
 assign qsfp_0_txc_1 = 8'hff;
 assign qsfp_0_txd_2 = 64'h0707070707070707;

example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v

@@ -356,8 +356,6 @@ assign user_led_g = ~led_reg[1:0];
 assign user_led_r = 1'b1;
 assign front_led = 2'b00;
 
-assign phy_reset_n = !rst;
-
 assign qsfp_0_txd_1 = 64'h0707070707070707;
 assign qsfp_0_txc_1 = 8'hff;
 assign qsfp_0_txd_2 = 64'h0707070707070707;

example/ATLYS/fpga/rtl/fpga.v

@@ -169,6 +169,8 @@ debounce_switch_inst (
         sw_int})
 );
 
+wire uart_rxd_int;
+
 sync_signal #(
     .WIDTH(1),
     .N(2)

example/AU280/fpga_10g/rtl/fpga_core.v

@@ -344,9 +344,6 @@ always @(posedge clk) begin
     end
 end
 
-//assign led = sw;
-assign led = led_reg;
-
 assign qsfp0_txd_2 = 64'h0707070707070707;
 assign qsfp0_txc_2 = 8'hff;
 assign qsfp0_txd_3 = 64'h0707070707070707;

example/Arty/fpga/rtl/fpga.v

@@ -202,6 +202,8 @@ debounce_switch_inst (
         sw_int})
 );
 
+wire uart_rxd_int;
+
 sync_signal #(
     .WIDTH(1),
     .N(2)

example/ExaNIC_X10/fpga/rtl/fpga_core.v

@@ -300,7 +300,7 @@ always @(posedge clk) begin
     end
 end
 
-assign led = led_reg;
+assign sma_led = led_reg;
 
 assign sfp_2_txd = 64'h0707070707070707;
 assign sfp_2_txc = 8'hff;

example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v

@@ -300,7 +300,7 @@ always @(posedge clk) begin
     end
 end
 
-assign led = led_reg;
+assign sma_led = led_reg;
 
 assign sfp_2_txd = 64'h0707070707070707;
 assign sfp_2_txc = 8'hff;

example/HTG9200/fpga_10g/rtl/fpga.v

@@ -160,12 +160,15 @@ module fpga (
 
 wire ref_clk_ibufg;
 
-wire clk_125mhz_mmcm_out;
-
 // Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
 wire clk_125mhz_int;
 wire rst_125mhz_int;
 
+// Internal 156.25 MHz clock
+wire clk_156mhz_int;
+wire rst_156mhz_int;
+
 wire mmcm_rst = ~btn[0];
 wire mmcm_locked;
 wire mmcm_clkfb;

example/NetFPGA_SUME/fpga/rtl/fpga.v

@@ -218,6 +218,13 @@ debounce_switch_inst (
 );
 
 // I2C
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_scl_t;
+wire i2c_sda_i;
+wire i2c_sda_o;
+wire i2c_sda_t;
+
 assign i2c_scl_i = i2c_scl;
 assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
 assign i2c_sda_i = i2c_sda;

example/NexysVideo/fpga/rtl/fpga.v

@@ -211,6 +211,8 @@ debounce_switch_inst (
         sw_int})
 );
 
+wire uart_rxd_int;
+
 sync_signal #(
     .WIDTH(1),
     .N(2)

example/S10MX_DK/fpga_10g/rtl/fpga.v

@@ -85,6 +85,9 @@ sync_reset_100mhz_inst (
     .out(rst_100mhz)
 );
 
+wire clk_156mhz_int;
+wire rst_156mhz_int;
+
 // XGMII 10G PHY
 assign qsfp0_modsel_l = 1'b0;
 assign qsfp0_reset_l = 1'b1;

example/ZCU102/fpga/rtl/fpga.v

@@ -281,6 +281,8 @@ assign rst_156mhz_int = sfp0_tx_rst_int;
 
 wire sfp0_rx_block_lock;
 wire sfp1_rx_block_lock;
+wire sfp2_rx_block_lock;
+wire sfp3_rx_block_lock;
 
 wire sfp_mgt_refclk_0;
 

example/fb2CG/fpga_10g/rtl/fpga.v

@@ -324,7 +324,7 @@ eth_xcvr_phy_wrapper #(
 )
 qsfp_0_phy_0_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
-    .xcvr_ctrl_rst(qsfp_0_reset),
+    .xcvr_ctrl_rst(qsfp_0_rst),
 
     // Common
     .xcvr_gtpowergood_out(qsfp_0_gtpowergood),
@@ -370,7 +370,7 @@ eth_xcvr_phy_wrapper #(
 )
 qsfp_0_phy_1_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
-    .xcvr_ctrl_rst(qsfp_0_reset),
+    .xcvr_ctrl_rst(qsfp_0_rst),
 
     // Common
     .xcvr_gtpowergood_out(),
@@ -416,7 +416,7 @@ eth_xcvr_phy_wrapper #(
 )
 qsfp_0_phy_2_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
-    .xcvr_ctrl_rst(qsfp_0_reset),
+    .xcvr_ctrl_rst(qsfp_0_rst),
 
     // Common
     .xcvr_gtpowergood_out(),
@@ -462,7 +462,7 @@ eth_xcvr_phy_wrapper #(
 )
 qsfp_0_phy_3_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
-    .xcvr_ctrl_rst(qsfp_0_reset),
+    .xcvr_ctrl_rst(qsfp_0_rst),
 
     // Common
     .xcvr_gtpowergood_out(),

example/fb2CG/fpga_10g/rtl/fpga_core.v

@@ -357,8 +357,6 @@ assign led_green = led_reg;
 assign led_bmc = 2'b00;
 assign led_exp = 2'b11;
 
-assign phy_reset_n = !rst;
-
 assign qsfp_0_txd_1 = 64'h0707070707070707;
 assign qsfp_0_txc_1 = 8'hff;
 assign qsfp_0_txd_2 = 64'h0707070707070707;