FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

Force AXIS RAM switch output FIFO into distributed RAM

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2024-01-28 16:38:38 -08:00
parent c6ecd770e7
commit 10b6d2f5bc
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
rtl/axis_ram_switch.v
View File

@ -912,11 +912,17 @@ generate
assign port_cmd_status_ready[m] = int_cmd_status_ready[m*M_COUNT+n];
end
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DATA_WIDTH-1:0] out_fifo_tdata[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg out_fifo_tlast[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [M_ID_WIDTH-1:0] out_fifo_tid[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [M_DEST_WIDTH-1:0] out_fifo_tdest[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [USER_WIDTH-1:0] out_fifo_tuser[31:0];
reg [5:0] out_fifo_data_wr_ptr_reg = 0;