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https://github.com/alexforencich/verilog-ethernet.git
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merged changes in axis
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commit
12744433de
@ -168,7 +168,7 @@ arb_inst (
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.grant_encoded(grant_encoded)
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.grant_encoded(grant_encoded)
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);
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);
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assign request = (s_axis_tvalid_reg & ~grant) | (s_axis_tvalid & grant);
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assign request = s_axis_tvalid | (s_axis_tvalid_reg & ~grant);
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assign acknowledge = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_ENABLE ? s_axis_tlast_reg : {S_COUNT{1'b1}});
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assign acknowledge = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_ENABLE ? s_axis_tlast_reg : {S_COUNT{1'b1}});
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always @* begin
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always @* begin
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@ -861,17 +861,20 @@ if (PAUSE_ENABLE) begin : pause
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always @(posedge m_clk) begin
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always @(posedge m_clk) begin
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if (FRAME_PAUSE) begin
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if (FRAME_PAUSE) begin
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if (m_axis_tvalid && m_axis_tready) begin
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if (pause_reg) begin
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if (m_axis_tlast) begin
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// paused; update pause status
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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end else if (m_axis_tvalid_out) begin
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// frame transfer; set frame bit
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pause_frame_reg <= 1'b1;
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if (m_axis_tready && m_axis_tlast) begin
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// end of frame; clear frame bit and update pause status
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pause_frame_reg <= 1'b0;
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pause_frame_reg <= 1'b0;
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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end else begin
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pause_frame_reg <= 1'b1;
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end
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end else begin
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if (!pause_frame_reg) begin
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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end
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end
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end else if (!pause_frame_reg) begin
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// idle; update pause status
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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end
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end
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end else begin
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end else begin
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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@ -517,17 +517,20 @@ if (PAUSE_ENABLE) begin : pause
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (FRAME_PAUSE) begin
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if (FRAME_PAUSE) begin
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if (m_axis_tvalid && m_axis_tready) begin
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if (pause_reg) begin
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if (m_axis_tlast) begin
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// paused; update pause status
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pause_reg <= pause_req;
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end else if (m_axis_tvalid_out) begin
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// frame transfer; set frame bit
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pause_frame_reg <= 1'b1;
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if (m_axis_tready && m_axis_tlast) begin
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// end of frame; clear frame bit and update pause status
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pause_frame_reg <= 1'b0;
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pause_frame_reg <= 1'b0;
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pause_reg <= pause_req;
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pause_reg <= pause_req;
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end else begin
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pause_frame_reg <= 1'b1;
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end
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end else begin
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if (!pause_frame_reg) begin
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pause_reg <= pause_req;
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end
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end
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end else if (!pause_frame_reg) begin
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// idle; update pause status
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pause_reg <= pause_req;
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end
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end
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end else begin
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end else begin
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pause_reg <= pause_req;
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pause_reg <= pause_req;
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