mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Clean up XGMII symbol generation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
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0d3f5fbbc4
commit
13c1872a42
@ -328,7 +328,8 @@ always @* begin
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s_empty_next = keep2empty(s_axis_tkeep);
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s_empty_next = keep2empty(s_axis_tkeep);
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xgmii_txd_next = {ETH_SFD, {3{ETH_PRE}}};
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xgmii_txd_next = {ETH_SFD, {3{ETH_PRE}}};
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xgmii_txc_next = 4'b0000;
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xgmii_txc_next = {CTRL_WIDTH{1'b0}};
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s_axis_tready_next = 1'b1;
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s_axis_tready_next = 1'b1;
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start_packet_next = 1'b1;
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start_packet_next = 1'b1;
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state_next = STATE_PAYLOAD;
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state_next = STATE_PAYLOAD;
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@ -345,7 +346,7 @@ always @* begin
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end
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end
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xgmii_txd_next = s_tdata_reg;
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xgmii_txd_next = s_tdata_reg;
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xgmii_txc_next = 4'b0000;
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xgmii_txc_next = {CTRL_WIDTH{1'b0}};
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s_tdata_next = s_axis_tdata_masked;
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s_tdata_next = s_axis_tdata_masked;
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s_empty_next = keep2empty(s_axis_tkeep);
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s_empty_next = keep2empty(s_axis_tkeep);
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@ -355,7 +356,7 @@ always @* begin
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s_axis_tready_next = 1'b0;
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s_axis_tready_next = 1'b0;
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if (s_axis_tuser[0]) begin
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if (s_axis_tuser[0]) begin
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xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
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xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
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xgmii_txc_next = 4'b1111;
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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ifg_count_next = 8'd10;
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ifg_count_next = 8'd10;
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state_next = STATE_IFG;
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state_next = STATE_IFG;
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end else begin
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end else begin
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@ -381,7 +382,7 @@ always @* begin
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end else begin
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end else begin
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// tvalid deassert, fail frame
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// tvalid deassert, fail frame
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xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
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xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
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xgmii_txc_next = 4'b1111;
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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ifg_count_next = 8'd10;
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ifg_count_next = 8'd10;
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error_underflow_next = 1'b1;
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error_underflow_next = 1'b1;
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state_next = STATE_WAIT_END;
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state_next = STATE_WAIT_END;
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@ -438,7 +439,7 @@ always @* begin
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s_axis_tready_next = 1'b0;
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s_axis_tready_next = 1'b0;
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM};
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM};
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xgmii_txc_next = 4'b1111;
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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if (ENABLE_DIC) begin
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if (ENABLE_DIC) begin
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if (ifg_count_next > 8'd3) begin
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if (ifg_count_next > 8'd3) begin
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@ -459,6 +460,11 @@ always @* begin
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end
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end
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STATE_IFG: begin
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STATE_IFG: begin
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// send IFG
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// send IFG
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// XGMII idle
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xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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if (ifg_count_reg > 8'd4) begin
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if (ifg_count_reg > 8'd4) begin
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ifg_count_next = ifg_count_reg - 8'd4;
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ifg_count_next = ifg_count_reg - 8'd4;
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end else begin
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end else begin
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@ -485,6 +491,10 @@ always @* begin
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// wait for end of frame
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// wait for end of frame
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s_axis_tready_next = 1'b1;
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s_axis_tready_next = 1'b1;
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// XGMII idle
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xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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if (ifg_count_reg > 8'd4) begin
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if (ifg_count_reg > 8'd4) begin
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ifg_count_next = ifg_count_reg - 8'd4;
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ifg_count_next = ifg_count_reg - 8'd4;
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end else begin
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end else begin
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@ -409,7 +409,7 @@ always @* begin
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end
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end
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xgmii_txd_next = s_tdata_reg;
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xgmii_txd_next = s_tdata_reg;
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xgmii_txc_next = 8'b00000000;
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xgmii_txc_next = {CTRL_WIDTH{1'b0}};
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s_tdata_next = s_axis_tdata_masked;
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s_tdata_next = s_axis_tdata_masked;
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s_empty_next = keep2empty(s_axis_tkeep);
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s_empty_next = keep2empty(s_axis_tkeep);
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@ -419,7 +419,7 @@ always @* begin
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s_axis_tready_next = 1'b0;
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s_axis_tready_next = 1'b0;
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if (s_axis_tuser[0]) begin
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if (s_axis_tuser[0]) begin
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
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xgmii_txc_next = 8'b11111111;
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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ifg_count_next = 8'd8;
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ifg_count_next = 8'd8;
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state_next = STATE_IFG;
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state_next = STATE_IFG;
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end else begin
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end else begin
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@ -445,7 +445,7 @@ always @* begin
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end else begin
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end else begin
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// tvalid deassert, fail frame
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// tvalid deassert, fail frame
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
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xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
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xgmii_txc_next = 8'b11111111;
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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ifg_count_next = 8'd8;
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ifg_count_next = 8'd8;
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error_underflow_next = 1'b1;
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error_underflow_next = 1'b1;
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state_next = STATE_WAIT_END;
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state_next = STATE_WAIT_END;
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@ -522,6 +522,11 @@ always @* begin
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end
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end
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STATE_IFG: begin
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STATE_IFG: begin
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// send IFG
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// send IFG
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// XGMII idle
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xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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if (ifg_count_reg > 8'd8) begin
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if (ifg_count_reg > 8'd8) begin
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ifg_count_next = ifg_count_reg - 8'd8;
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ifg_count_next = ifg_count_reg - 8'd8;
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end else begin
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end else begin
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@ -557,6 +562,10 @@ always @* begin
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// wait for end of frame
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// wait for end of frame
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s_axis_tready_next = 1'b1;
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s_axis_tready_next = 1'b1;
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// XGMII idle
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xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
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xgmii_txc_next = {CTRL_WIDTH{1'b1}};
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if (ifg_count_reg > 8'd8) begin
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if (ifg_count_reg > 8'd8) begin
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ifg_count_next = ifg_count_reg - 8'd8;
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ifg_count_next = ifg_count_reg - 8'd8;
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end else begin
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end else begin
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