FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

Update parametrization

Browse Source
This commit is contained in:
Alex Forencich 2016-01-08 01:30:00 -08:00
parent 9c01e114b4
commit 152486bebd
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
rtl/gmii_phy_if.v
View File

@ -31,7 +31,8 @@ THE SOFTWARE.
*/
module gmii_phy_if #
(
parameter TARGET_XILINX = 0
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC"
)
(
input wire clk,
@ -70,7 +71,7 @@ wire phy_gmii_tx_clk_int;
generate
if (TARGET_XILINX) begin
if (TARGET == "XILINX") begin
// use Xilinx clocking primitives