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Code Issues Projects Releases Wiki Activity

Update example designs

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This commit is contained in:
Alex Forencich 2019-07-18 17:13:47 -07:00
parent 3bd7be44fa
commit 16e5ec2106
56 changed files with 99 additions and 59 deletions
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1
example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -45,6 +45,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -378,9 +378,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -616,7 +616,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -45,6 +45,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -378,9 +378,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -616,7 +616,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/ATLYS/fpga/fpga/Makefile
View File

@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

6
example/ATLYS/fpga/rtl/fpga_core.v
View File

@ -311,9 +311,9 @@ eth_mac_1g_gmii_fifo #(
.CLOCK_INPUT_STYLE("BUFIO2"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -541,7 +541,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/ATLYS/fpga/tb/test_fpga_core.py
View File

@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/Arty/fpga/fpga/Makefile
View File

@ -39,6 +39,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/Arty/fpga/rtl/fpga_core.v
View File

@ -321,9 +321,9 @@ eth_mac_mii_fifo #(
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -548,7 +548,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/Arty/fpga/tb/test_fpga_core.py
View File

@ -66,6 +66,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/DE5-Net/fpga/fpga/Makefile
View File

@ -40,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += cores/phy/phy.qip
SYN_FILES += cores/phy_reconfig/phy_reconfig.qip

6
example/DE5-Net/fpga/rtl/fpga_core.v
View File

@ -329,9 +329,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -567,7 +567,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/DE5-Net/fpga/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

8
example/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -309,8 +309,10 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_ADDR_WIDTH(9)
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(sfp_1_rx_clk),
@ -545,7 +547,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -65,6 +65,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/HXT100G/fpga/fpga/Makefile
View File

@ -43,6 +43,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

6
example/HXT100G/fpga/rtl/fpga_core.v
View File

@ -473,9 +473,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -711,7 +711,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/HXT100G/fpga/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/HXT100G/fpga_cxpt16/fpga/Makefile
View File

@ -26,6 +26,7 @@ SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_crosspoint.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

4
example/HXT100G/fpga_cxpt16/rtl/fpga_core.v
View File

@ -270,9 +270,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_fifo_inst (

1
example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py
View File

@ -44,6 +44,7 @@ srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_crosspoint.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/KC705/fpga_gmii/fpga/Makefile
View File

@ -41,6 +41,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/KC705/fpga_gmii/rtl/fpga_core.v
View File

@ -315,9 +315,9 @@ eth_mac_1g_gmii_fifo #(
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -545,7 +545,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/KC705/fpga_gmii/tb/test_fpga_core.py
View File

@ -68,6 +68,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/ML605/fpga_gmii/fpga_130t/Makefile
View File

@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

1
example/ML605/fpga_gmii/fpga_240t/Makefile
View File

@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

6
example/ML605/fpga_gmii/rtl/fpga_core.v
View File

@ -324,9 +324,9 @@ eth_mac_1g_gmii_fifo #(
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -554,7 +554,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/ML605/fpga_gmii/tb/test_fpga_core.py
View File

@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/ML605/fpga_rgmii/fpga_130t/Makefile
View File

@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

1
example/ML605/fpga_rgmii/fpga_240t/Makefile
View File

@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

6
example/ML605/fpga_rgmii/rtl/fpga_core.v
View File

@ -323,9 +323,9 @@ eth_mac_1g_rgmii_fifo #(
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -551,7 +551,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/ML605/fpga_rgmii/tb/test_fpga_core.py
View File

@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/ML605/fpga_sgmii/fpga_130t/Makefile
View File

@ -40,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v

1
example/ML605/fpga_sgmii/fpga_240t/Makefile
View File

@ -40,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v

6
example/ML605/fpga_sgmii/rtl/fpga_core.v
View File

@ -318,9 +318,9 @@ assign uart_cts = 0;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -551,7 +551,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/ML605/fpga_sgmii/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/NexysVideo/fpga/fpga/Makefile
View File

@ -42,6 +42,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/NexysVideo/fpga/rtl/fpga_core.v
View File

@ -312,9 +312,9 @@ eth_mac_1g_rgmii_fifo #(
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -540,7 +540,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/NexysVideo/fpga/tb/test_fpga_core.py
View File

@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/VCU108/fpga_10g/fpga/Makefile
View File

@ -52,6 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

10
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -375,9 +375,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -449,9 +449,9 @@ wire gig_tx_axis_tuser_64;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
@ -824,7 +824,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -73,6 +73,7 @@ srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_register.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/VCU108/fpga_1g/fpga/Makefile
View File

@ -36,6 +36,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/VCU108/fpga_1g/rtl/fpga_core.v
View File

@ -309,9 +309,9 @@ assign uart_rts = 0;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -542,7 +542,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/VCU108/fpga_1g/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/VCU118/fpga_10g/fpga/Makefile
View File

@ -53,6 +53,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

10
example/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -416,9 +416,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -490,9 +490,9 @@ wire gig_tx_axis_tuser_64;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
@ -865,7 +865,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -73,6 +73,7 @@ srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_register.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/VCU118/fpga_1g/fpga/Makefile
View File

@ -37,6 +37,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

6
example/VCU118/fpga_1g/rtl/fpga_core.v
View File

@ -309,9 +309,9 @@ assign uart_rts = 0;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
@ -542,7 +542,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(12),
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),

1
example/VCU118/fpga_1g/tb/test_fpga_core.py
View File

@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

1
example/VCU118/fpga_25g/fpga/Makefile
View File

@ -53,6 +53,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
# XDC files
XDC_FILES = fpga.xdc

10
example/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -416,9 +416,9 @@ eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
@ -490,9 +490,9 @@ wire gig_tx_axis_tuser_64;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FIFO_DEPTH(4906),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_DEPTH(4906),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
@ -865,7 +865,7 @@ udp_complete_inst (
);
axis_fifo #(
.ADDR_WIDTH(10),
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),

1
example/VCU118/fpga_25g/tb/test_fpga_core.py
View File

@ -73,6 +73,7 @@ srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_register.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)