From 16e5ec2106ec2da40490374e90ea44b91c2864fb Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 18 Jul 2019 17:13:47 -0700 Subject: [PATCH] Update example designs --- example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile | 1 + example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 6 +++--- example/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py | 1 + example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 1 + example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 6 +++--- example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py | 1 + example/ATLYS/fpga/fpga/Makefile | 1 + example/ATLYS/fpga/rtl/fpga_core.v | 6 +++--- example/ATLYS/fpga/tb/test_fpga_core.py | 1 + example/Arty/fpga/fpga/Makefile | 1 + example/Arty/fpga/rtl/fpga_core.v | 6 +++--- example/Arty/fpga/tb/test_fpga_core.py | 1 + example/DE5-Net/fpga/fpga/Makefile | 1 + example/DE5-Net/fpga/rtl/fpga_core.v | 6 +++--- example/DE5-Net/fpga/tb/test_fpga_core.py | 1 + example/ExaNIC_X10/fpga/rtl/fpga_core.v | 8 +++++--- example/ExaNIC_X10/fpga/tb/test_fpga_core.py | 1 + example/HXT100G/fpga/fpga/Makefile | 1 + example/HXT100G/fpga/rtl/fpga_core.v | 6 +++--- example/HXT100G/fpga/tb/test_fpga_core.py | 1 + example/HXT100G/fpga_cxpt16/fpga/Makefile | 1 + example/HXT100G/fpga_cxpt16/rtl/fpga_core.v | 4 ++-- example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py | 1 + example/KC705/fpga_gmii/fpga/Makefile | 1 + example/KC705/fpga_gmii/rtl/fpga_core.v | 6 +++--- example/KC705/fpga_gmii/tb/test_fpga_core.py | 1 + example/ML605/fpga_gmii/fpga_130t/Makefile | 1 + example/ML605/fpga_gmii/fpga_240t/Makefile | 1 + example/ML605/fpga_gmii/rtl/fpga_core.v | 6 +++--- example/ML605/fpga_gmii/tb/test_fpga_core.py | 1 + example/ML605/fpga_rgmii/fpga_130t/Makefile | 1 + example/ML605/fpga_rgmii/fpga_240t/Makefile | 1 + example/ML605/fpga_rgmii/rtl/fpga_core.v | 6 +++--- example/ML605/fpga_rgmii/tb/test_fpga_core.py | 1 + example/ML605/fpga_sgmii/fpga_130t/Makefile | 1 + example/ML605/fpga_sgmii/fpga_240t/Makefile | 1 + example/ML605/fpga_sgmii/rtl/fpga_core.v | 6 +++--- example/ML605/fpga_sgmii/tb/test_fpga_core.py | 1 + example/NexysVideo/fpga/fpga/Makefile | 1 + example/NexysVideo/fpga/rtl/fpga_core.v | 6 +++--- example/NexysVideo/fpga/tb/test_fpga_core.py | 1 + example/VCU108/fpga_10g/fpga/Makefile | 1 + example/VCU108/fpga_10g/rtl/fpga_core.v | 10 +++++----- example/VCU108/fpga_10g/tb/test_fpga_core.py | 1 + example/VCU108/fpga_1g/fpga/Makefile | 1 + example/VCU108/fpga_1g/rtl/fpga_core.v | 6 +++--- example/VCU108/fpga_1g/tb/test_fpga_core.py | 1 + example/VCU118/fpga_10g/fpga/Makefile | 1 + example/VCU118/fpga_10g/rtl/fpga_core.v | 10 +++++----- example/VCU118/fpga_10g/tb/test_fpga_core.py | 1 + example/VCU118/fpga_1g/fpga/Makefile | 1 + example/VCU118/fpga_1g/rtl/fpga_core.v | 6 +++--- example/VCU118/fpga_1g/tb/test_fpga_core.py | 1 + example/VCU118/fpga_25g/fpga/Makefile | 1 + example/VCU118/fpga_25g/rtl/fpga_core.v | 10 +++++----- example/VCU118/fpga_25g/tb/test_fpga_core.py | 1 + 56 files changed, 99 insertions(+), 59 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index 1a17dbda..88123ba3 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -45,6 +45,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 93f5ddc4..28390470 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -378,9 +378,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -616,7 +616,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index 35b21e22..66f3dca7 100755 --- a/example/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 1a17dbda..88123ba3 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -45,6 +45,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 93f5ddc4..8cfd5602 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -378,9 +378,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4096), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4096), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -616,7 +616,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py index 35b21e22..66f3dca7 100755 --- a/example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/ATLYS/fpga/fpga/Makefile b/example/ATLYS/fpga/fpga/Makefile index 956dac9d..1a49e461 100644 --- a/example/ATLYS/fpga/fpga/Makefile +++ b/example/ATLYS/fpga/fpga/Makefile @@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v #SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v # UCF files diff --git a/example/ATLYS/fpga/rtl/fpga_core.v b/example/ATLYS/fpga/rtl/fpga_core.v index 2fb71402..d8bb8e74 100644 --- a/example/ATLYS/fpga/rtl/fpga_core.v +++ b/example/ATLYS/fpga/rtl/fpga_core.v @@ -311,9 +311,9 @@ eth_mac_1g_gmii_fifo #( .CLOCK_INPUT_STYLE("BUFIO2"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -541,7 +541,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/ATLYS/fpga/tb/test_fpga_core.py b/example/ATLYS/fpga/tb/test_fpga_core.py index 081281ea..37eca044 100755 --- a/example/ATLYS/fpga/tb/test_fpga_core.py +++ b/example/ATLYS/fpga/tb/test_fpga_core.py @@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/Arty/fpga/fpga/Makefile b/example/Arty/fpga/fpga/Makefile index 36d5be2e..64f0a977 100644 --- a/example/Arty/fpga/fpga/Makefile +++ b/example/Arty/fpga/fpga/Makefile @@ -39,6 +39,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/Arty/fpga/rtl/fpga_core.v b/example/Arty/fpga/rtl/fpga_core.v index f13193e9..5e919748 100644 --- a/example/Arty/fpga/rtl/fpga_core.v +++ b/example/Arty/fpga/rtl/fpga_core.v @@ -321,9 +321,9 @@ eth_mac_mii_fifo #( .CLOCK_INPUT_STYLE("BUFR"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -548,7 +548,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/Arty/fpga/tb/test_fpga_core.py b/example/Arty/fpga/tb/test_fpga_core.py index 07e9f84c..193eefc9 100755 --- a/example/Arty/fpga/tb/test_fpga_core.py +++ b/example/Arty/fpga/tb/test_fpga_core.py @@ -66,6 +66,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/DE5-Net/fpga/fpga/Makefile b/example/DE5-Net/fpga/fpga/Makefile index 4f880892..bd8beb0e 100644 --- a/example/DE5-Net/fpga/fpga/Makefile +++ b/example/DE5-Net/fpga/fpga/Makefile @@ -40,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += cores/phy/phy.qip SYN_FILES += cores/phy_reconfig/phy_reconfig.qip diff --git a/example/DE5-Net/fpga/rtl/fpga_core.v b/example/DE5-Net/fpga/rtl/fpga_core.v index 56a15431..6a056b97 100644 --- a/example/DE5-Net/fpga/rtl/fpga_core.v +++ b/example/DE5-Net/fpga/rtl/fpga_core.v @@ -329,9 +329,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -567,7 +567,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/DE5-Net/fpga/tb/test_fpga_core.py b/example/DE5-Net/fpga/tb/test_fpga_core.py index 5a4a121d..326d8b68 100755 --- a/example/DE5-Net/fpga/tb/test_fpga_core.py +++ b/example/DE5-Net/fpga/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/ExaNIC_X10/fpga/rtl/fpga_core.v b/example/ExaNIC_X10/fpga/rtl/fpga_core.v index 952c0f39..89d2dea5 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -309,8 +309,10 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), - .RX_FIFO_ADDR_WIDTH(9) + .TX_FIFO_DEPTH(4906), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4906), + .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( .rx_clk(sfp_1_rx_clk), @@ -545,7 +547,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/ExaNIC_X10/fpga/tb/test_fpga_core.py b/example/ExaNIC_X10/fpga/tb/test_fpga_core.py index c4e47a95..5bfb012f 100755 --- a/example/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -65,6 +65,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/HXT100G/fpga/fpga/Makefile b/example/HXT100G/fpga/fpga/Makefile index d1c3e8b5..df6cd4ed 100644 --- a/example/HXT100G/fpga/fpga/Makefile +++ b/example/HXT100G/fpga/fpga/Makefile @@ -43,6 +43,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v diff --git a/example/HXT100G/fpga/rtl/fpga_core.v b/example/HXT100G/fpga/rtl/fpga_core.v index 4efe3413..dc7e9d32 100644 --- a/example/HXT100G/fpga/rtl/fpga_core.v +++ b/example/HXT100G/fpga/rtl/fpga_core.v @@ -473,9 +473,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -711,7 +711,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/HXT100G/fpga/tb/test_fpga_core.py b/example/HXT100G/fpga/tb/test_fpga_core.py index dac66e78..22985bbe 100755 --- a/example/HXT100G/fpga/tb/test_fpga_core.py +++ b/example/HXT100G/fpga/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/HXT100G/fpga_cxpt16/fpga/Makefile b/example/HXT100G/fpga_cxpt16/fpga/Makefile index d2771adf..ae01045d 100644 --- a/example/HXT100G/fpga_cxpt16/fpga/Makefile +++ b/example/HXT100G/fpga_cxpt16/fpga/Makefile @@ -26,6 +26,7 @@ SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v SYN_FILES += lib/eth/lib/axis/rtl/axis_crosspoint.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v b/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v index ccf2b23b..3ce00330 100644 --- a/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v +++ b/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v @@ -270,9 +270,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_fifo_inst ( diff --git a/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py b/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py index 5957dc95..ac672bd5 100755 --- a/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py +++ b/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py @@ -44,6 +44,7 @@ srcs.append("../lib/eth/rtl/eth_axis_rx_64.v") srcs.append("../lib/eth/rtl/eth_axis_tx_64.v") srcs.append("../lib/eth/lib/axis/rtl/axis_crosspoint.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/KC705/fpga_gmii/fpga/Makefile b/example/KC705/fpga_gmii/fpga/Makefile index 7231fad4..495c8161 100644 --- a/example/KC705/fpga_gmii/fpga/Makefile +++ b/example/KC705/fpga_gmii/fpga/Makefile @@ -41,6 +41,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/KC705/fpga_gmii/rtl/fpga_core.v b/example/KC705/fpga_gmii/rtl/fpga_core.v index cd2002c8..e9092488 100644 --- a/example/KC705/fpga_gmii/rtl/fpga_core.v +++ b/example/KC705/fpga_gmii/rtl/fpga_core.v @@ -315,9 +315,9 @@ eth_mac_1g_gmii_fifo #( .CLOCK_INPUT_STYLE("BUFR"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -545,7 +545,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/KC705/fpga_gmii/tb/test_fpga_core.py b/example/KC705/fpga_gmii/tb/test_fpga_core.py index 18864b43..2eb05f15 100755 --- a/example/KC705/fpga_gmii/tb/test_fpga_core.py +++ b/example/KC705/fpga_gmii/tb/test_fpga_core.py @@ -68,6 +68,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/ML605/fpga_gmii/fpga_130t/Makefile b/example/ML605/fpga_gmii/fpga_130t/Makefile index cdecade0..a09a0023 100644 --- a/example/ML605/fpga_gmii/fpga_130t/Makefile +++ b/example/ML605/fpga_gmii/fpga_130t/Makefile @@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v #SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v # UCF files diff --git a/example/ML605/fpga_gmii/fpga_240t/Makefile b/example/ML605/fpga_gmii/fpga_240t/Makefile index 54a553c0..287bf525 100644 --- a/example/ML605/fpga_gmii/fpga_240t/Makefile +++ b/example/ML605/fpga_gmii/fpga_240t/Makefile @@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v #SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v # UCF files diff --git a/example/ML605/fpga_gmii/rtl/fpga_core.v b/example/ML605/fpga_gmii/rtl/fpga_core.v index 9db20505..b2115154 100644 --- a/example/ML605/fpga_gmii/rtl/fpga_core.v +++ b/example/ML605/fpga_gmii/rtl/fpga_core.v @@ -324,9 +324,9 @@ eth_mac_1g_gmii_fifo #( .CLOCK_INPUT_STYLE("BUFR"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -554,7 +554,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/ML605/fpga_gmii/tb/test_fpga_core.py b/example/ML605/fpga_gmii/tb/test_fpga_core.py index f52a00a5..bffc9127 100755 --- a/example/ML605/fpga_gmii/tb/test_fpga_core.py +++ b/example/ML605/fpga_gmii/tb/test_fpga_core.py @@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/ML605/fpga_rgmii/fpga_130t/Makefile b/example/ML605/fpga_rgmii/fpga_130t/Makefile index b315b1c0..3b6b054b 100644 --- a/example/ML605/fpga_rgmii/fpga_130t/Makefile +++ b/example/ML605/fpga_rgmii/fpga_130t/Makefile @@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v #SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v # UCF files diff --git a/example/ML605/fpga_rgmii/fpga_240t/Makefile b/example/ML605/fpga_rgmii/fpga_240t/Makefile index 4d46cec2..bb238a7d 100644 --- a/example/ML605/fpga_rgmii/fpga_240t/Makefile +++ b/example/ML605/fpga_rgmii/fpga_240t/Makefile @@ -46,6 +46,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v #SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v # UCF files diff --git a/example/ML605/fpga_rgmii/rtl/fpga_core.v b/example/ML605/fpga_rgmii/rtl/fpga_core.v index d01a4034..164b3dd6 100644 --- a/example/ML605/fpga_rgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_rgmii/rtl/fpga_core.v @@ -323,9 +323,9 @@ eth_mac_1g_rgmii_fifo #( .USE_CLK90("TRUE"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -551,7 +551,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/ML605/fpga_rgmii/tb/test_fpga_core.py b/example/ML605/fpga_rgmii/tb/test_fpga_core.py index 5b03aa9a..c0eaf984 100755 --- a/example/ML605/fpga_rgmii/tb/test_fpga_core.py +++ b/example/ML605/fpga_rgmii/tb/test_fpga_core.py @@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/ML605/fpga_sgmii/fpga_130t/Makefile b/example/ML605/fpga_sgmii/fpga_130t/Makefile index 74718cc8..ba289342 100644 --- a/example/ML605/fpga_sgmii/fpga_130t/Makefile +++ b/example/ML605/fpga_sgmii/fpga_130t/Makefile @@ -40,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v diff --git a/example/ML605/fpga_sgmii/fpga_240t/Makefile b/example/ML605/fpga_sgmii/fpga_240t/Makefile index 4fe5d60e..70576843 100644 --- a/example/ML605/fpga_sgmii/fpga_240t/Makefile +++ b/example/ML605/fpga_sgmii/fpga_240t/Makefile @@ -40,6 +40,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v diff --git a/example/ML605/fpga_sgmii/rtl/fpga_core.v b/example/ML605/fpga_sgmii/rtl/fpga_core.v index f699350d..02f3e385 100644 --- a/example/ML605/fpga_sgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_sgmii/rtl/fpga_core.v @@ -318,9 +318,9 @@ assign uart_cts = 0; eth_mac_1g_fifo #( .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -551,7 +551,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/ML605/fpga_sgmii/tb/test_fpga_core.py b/example/ML605/fpga_sgmii/tb/test_fpga_core.py index 259f76a4..20224304 100755 --- a/example/ML605/fpga_sgmii/tb/test_fpga_core.py +++ b/example/ML605/fpga_sgmii/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/NexysVideo/fpga/fpga/Makefile b/example/NexysVideo/fpga/fpga/Makefile index b54be330..6f07e8e7 100644 --- a/example/NexysVideo/fpga/fpga/Makefile +++ b/example/NexysVideo/fpga/fpga/Makefile @@ -42,6 +42,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/NexysVideo/fpga/rtl/fpga_core.v b/example/NexysVideo/fpga/rtl/fpga_core.v index 96e4a83a..68fae9ee 100644 --- a/example/NexysVideo/fpga/rtl/fpga_core.v +++ b/example/NexysVideo/fpga/rtl/fpga_core.v @@ -312,9 +312,9 @@ eth_mac_1g_rgmii_fifo #( .USE_CLK90("TRUE"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -540,7 +540,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/NexysVideo/fpga/tb/test_fpga_core.py b/example/NexysVideo/fpga/tb/test_fpga_core.py index c320ac26..a1168790 100755 --- a/example/NexysVideo/fpga/tb/test_fpga_core.py +++ b/example/NexysVideo/fpga/tb/test_fpga_core.py @@ -69,6 +69,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/VCU108/fpga_10g/fpga/Makefile b/example/VCU108/fpga_10g/fpga/Makefile index de36e54d..a25a7297 100644 --- a/example/VCU108/fpga_10g/fpga/Makefile +++ b/example/VCU108/fpga_10g/fpga/Makefile @@ -52,6 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index 16284a70..5f3b34dc 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -375,9 +375,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -449,9 +449,9 @@ wire gig_tx_axis_tuser_64; eth_mac_1g_fifo #( .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_1g_inst ( @@ -824,7 +824,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.py b/example/VCU108/fpga_10g/tb/test_fpga_core.py index 92c8db29..46592e0e 100755 --- a/example/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_10g/tb/test_fpga_core.py @@ -73,6 +73,7 @@ srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v") srcs.append("../lib/eth/lib/axis/rtl/axis_register.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/VCU108/fpga_1g/fpga/Makefile b/example/VCU108/fpga_1g/fpga/Makefile index ba7eadc0..28179b81 100644 --- a/example/VCU108/fpga_1g/fpga/Makefile +++ b/example/VCU108/fpga_1g/fpga/Makefile @@ -36,6 +36,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v index f2cf9cc5..e2cd9028 100644 --- a/example/VCU108/fpga_1g/rtl/fpga_core.v +++ b/example/VCU108/fpga_1g/rtl/fpga_core.v @@ -309,9 +309,9 @@ assign uart_rts = 0; eth_mac_1g_fifo #( .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -542,7 +542,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/VCU108/fpga_1g/tb/test_fpga_core.py b/example/VCU108/fpga_1g/tb/test_fpga_core.py index 97523fc5..5e2d1bee 100755 --- a/example/VCU108/fpga_1g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_1g/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/VCU118/fpga_10g/fpga/Makefile b/example/VCU118/fpga_10g/fpga/Makefile index 807cc1ed..de280200 100644 --- a/example/VCU118/fpga_10g/fpga/Makefile +++ b/example/VCU118/fpga_10g/fpga/Makefile @@ -53,6 +53,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/VCU118/fpga_10g/rtl/fpga_core.v b/example/VCU118/fpga_10g/rtl/fpga_core.v index a523e3af..c97a82f5 100644 --- a/example/VCU118/fpga_10g/rtl/fpga_core.v +++ b/example/VCU118/fpga_10g/rtl/fpga_core.v @@ -416,9 +416,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -490,9 +490,9 @@ wire gig_tx_axis_tuser_64; eth_mac_1g_fifo #( .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_1g_inst ( @@ -865,7 +865,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/VCU118/fpga_10g/tb/test_fpga_core.py b/example/VCU118/fpga_10g/tb/test_fpga_core.py index 00ed0dd0..057b7fc6 100755 --- a/example/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/example/VCU118/fpga_10g/tb/test_fpga_core.py @@ -73,6 +73,7 @@ srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v") srcs.append("../lib/eth/lib/axis/rtl/axis_register.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/VCU118/fpga_1g/fpga/Makefile b/example/VCU118/fpga_1g/fpga/Makefile index f5849ac8..0c5e52d7 100644 --- a/example/VCU118/fpga_1g/fpga/Makefile +++ b/example/VCU118/fpga_1g/fpga/Makefile @@ -37,6 +37,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/VCU118/fpga_1g/rtl/fpga_core.v b/example/VCU118/fpga_1g/rtl/fpga_core.v index f2cf9cc5..e2cd9028 100644 --- a/example/VCU118/fpga_1g/rtl/fpga_core.v +++ b/example/VCU118/fpga_1g/rtl/fpga_core.v @@ -309,9 +309,9 @@ assign uart_rts = 0; eth_mac_1g_fifo #( .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_inst ( @@ -542,7 +542,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(12), + .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), diff --git a/example/VCU118/fpga_1g/tb/test_fpga_core.py b/example/VCU118/fpga_1g/tb/test_fpga_core.py index 97523fc5..5e2d1bee 100755 --- a/example/VCU118/fpga_1g/tb/test_fpga_core.py +++ b/example/VCU118/fpga_1g/tb/test_fpga_core.py @@ -63,6 +63,7 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs) diff --git a/example/VCU118/fpga_25g/fpga/Makefile b/example/VCU118/fpga_25g/fpga/Makefile index 807cc1ed..de280200 100644 --- a/example/VCU118/fpga_25g/fpga/Makefile +++ b/example/VCU118/fpga_25g/fpga/Makefile @@ -53,6 +53,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # XDC files XDC_FILES = fpga.xdc diff --git a/example/VCU118/fpga_25g/rtl/fpga_core.v b/example/VCU118/fpga_25g/rtl/fpga_core.v index a523e3af..c97a82f5 100644 --- a/example/VCU118/fpga_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_25g/rtl/fpga_core.v @@ -416,9 +416,9 @@ eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(9), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(9), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( @@ -490,9 +490,9 @@ wire gig_tx_axis_tuser_64; eth_mac_1g_fifo #( .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), - .TX_FIFO_ADDR_WIDTH(12), + .TX_FIFO_DEPTH(4906), .TX_FRAME_FIFO(1), - .RX_FIFO_ADDR_WIDTH(12), + .RX_FIFO_DEPTH(4906), .RX_FRAME_FIFO(1) ) eth_mac_1g_inst ( @@ -865,7 +865,7 @@ udp_complete_inst ( ); axis_fifo #( - .ADDR_WIDTH(10), + .DEPTH(8192), .DATA_WIDTH(64), .KEEP_ENABLE(1), .KEEP_WIDTH(8), diff --git a/example/VCU118/fpga_25g/tb/test_fpga_core.py b/example/VCU118/fpga_25g/tb/test_fpga_core.py index 00ed0dd0..057b7fc6 100755 --- a/example/VCU118/fpga_25g/tb/test_fpga_core.py +++ b/example/VCU118/fpga_25g/tb/test_fpga_core.py @@ -73,6 +73,7 @@ srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v") srcs.append("../lib/eth/lib/axis/rtl/axis_register.v") srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") srcs.append("%s.v" % testbench) src = ' '.join(srcs)