mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Default FIFO size at least 2 MTU (3000 bytes)
This commit is contained in:
parent
6a012c992b
commit
16fec34ddc
@ -33,8 +33,8 @@ module eth_mac_1g_fifo #
|
||||
(
|
||||
parameter ENABLE_PADDING = 1,
|
||||
parameter MIN_FRAME_LENGTH = 64,
|
||||
parameter TX_FIFO_ADDR_WIDTH = 9,
|
||||
parameter RX_FIFO_ADDR_WIDTH = 9
|
||||
parameter TX_FIFO_ADDR_WIDTH = 12,
|
||||
parameter RX_FIFO_ADDR_WIDTH = 12
|
||||
)
|
||||
(
|
||||
input wire rx_clk,
|
||||
|
Loading…
x
Reference in New Issue
Block a user