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https://github.com/alexforencich/verilog-ethernet.git
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Add XGMII endpoint module
This commit is contained in:
Alex Forencich
parent
73bebaba46
commit
17edcfe88e
262
tb/xgmii_ep.py
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262
tb/xgmii_ep.py
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"""
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Copyright (c) 2015 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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class XGMIIFrame(object):
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def __init__(self, data=b'', error=None, ctrl=None):
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self.data = b''
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self.error = None
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self.ctrl = None
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if type(data) is XGMIIFrame:
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self.data = data.data
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self.error = data.error
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self.ctrl = data.ctrl
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else:
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self.data = bytearray(data)
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def build(self):
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if self.data is None:
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return
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f = list(self.data)
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ctrl = []
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error = []
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d = []
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c = []
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i = 0
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assert_error = False
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if (type(self.error) is int or type(self.error) is bool) and self.error:
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assert_error = True
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error = [0]*len(self.data)
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error[-1] = 1
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elif self.error is None:
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error = [0]*len(self.data)
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else:
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error = list(self.error)
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if self.ctrl is None:
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ctrl = [0]*len(self.data)
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else:
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ctrl = list(self.ctrl)
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assert len(ctrl) == len(f)
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assert len(ctrl) == len(f)
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for i in range(len(f)):
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if error[i]:
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f[i] = 0xfe
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ctrl[i] = 1
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i = 0
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while len(f) > 0:
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d.append(f.pop(0))
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c.append(ctrl[i])
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i += 1
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return d, c
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def parse(self, d, c):
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if d is None or c is None:
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return
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self.data = bytearray(d)
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self.ctrl = c
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self.error = [0]*len(self.data)
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for i in range(len(self.data)):
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if c[i] and d[i] == 0xfe:
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self.error[i] = 1
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def __eq__(self, other):
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if type(other) is XGMIIFrame:
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return self.data == other.data
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def __repr__(self):
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return 'XGMIIFrame(data=%s, error=%s, ctrl=%s)' % (repr(self.data), repr(self.error), repr(self.ctrl))
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def __iter__(self):
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return self.data.__iter__()
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def XGMIISource(clk, rst,
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txd,
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txc,
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fifo=None,
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name=None):
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@instance
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def logic():
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frame = None
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dl = []
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cl = []
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ifg_cnt = 0
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deficit_idle_cnt = 0
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nt = False
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while True:
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yield clk.posedge, rst.posedge
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if rst:
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frame = None
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txd.next = 0x0707070707070707
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txc.next = 0xff
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dl = []
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cl = []
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ifg_cnt = 0
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deficit_idle_cnt = 0
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nt = False
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else:
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if ifg_cnt > 7:
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ifg_cnt -= 8
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txd.next = 0x0707070707070707
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txc.next = 0xff
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elif len(dl) > 0 or nt:
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d = 0
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c = 0
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for i in range(8):
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if len(dl) > 0:
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d |= dl.pop(0) << (8*i)
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c |= cl.pop(0) << i
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nt = True
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else:
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if nt:
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d |= 0xfd << (8*i)
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nt = False
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ifg_cnt = 12 - (8-i) + deficit_idle_cnt
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else:
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d |= 0x07 << (8*i)
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c |= 1 << i
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txd.next = d
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txc.next = c
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elif not fifo.empty():
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frame = XGMIIFrame(fifo.get())
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dl, cl = frame.build()
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if name is not None:
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print("[%s] Sending frame %s" % (name, repr(frame)))
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if ifg_cnt >= 4:
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deficit_idle_cnt = ifg_cnt - 4
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else:
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deficit_idle_cnt = ifg_cnt
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ifg_cnt = 0
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assert len(dl) > 0
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assert dl.pop(0) == 0x55
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cl.pop(0)
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k = 1
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d = 0xfb
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c = 1
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if ifg_cnt > 0:
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k = 5
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d = 0xfb07070707
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c = 0x1f
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for i in range(k,8):
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if len(dl) > 0:
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d |= dl.pop(0) << (8*i)
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c |= cl.pop(0) << i
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nt = True
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else:
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if nt:
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d |= 0xfd << (8*i)
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nt = False
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else:
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d |= 0x07 << (8*i)
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c |= 1 << i
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txd.next = d
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txc.next = c
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else:
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ifg_cnt = 0
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deficit_idle_cnt = 0
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txd.next = 0x0707070707070707
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txc.next = 0xff
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return logic
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def XGMIISink(clk, rst,
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rxd,
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rxc,
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fifo=None,
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name=None):
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@instance
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def logic():
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frame = None
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d = []
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c = []
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while True:
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yield clk.posedge, rst.posedge
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if rst:
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frame = None
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d = []
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c = []
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else:
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if frame is None:
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if rxc & 1 and rxd & 0xff == 0xfb:
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# start in lane 0
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frame = XGMIIFrame()
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d = [0x55]
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c = [0]
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for i in range(1,8):
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d.append((int(rxd) >> (8*i)) & 0xff)
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c.append((int(rxc) >> i) & 1)
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elif (rxc >> 4) & 1 and (rxd >> 32) & 0xff == 0xfb:
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# start in lane 4
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frame = XGMIIFrame()
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d = [0x55]
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c = [0]
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for i in range(5,8):
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d.append((int(rxd) >> (8*i)) & 0xff)
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c.append((int(rxc) >> i) & 1)
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else:
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for i in range(8):
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if (rxc >> i) & 1 and (rxd >> (8*i)) & 0xff == 0xfd:
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# terminate
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frame.parse(d, c)
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if fifo is not None:
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fifo.put(frame)
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if name is not None:
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print("[%s] Got frame %s" % (name, repr(frame)))
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frame = None
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d = []
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c = []
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break
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else:
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d.append((int(rxd) >> (8*i)) & 0xff)
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c.append((int(rxc) >> i) & 1)
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return logic
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