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https://github.com/alexforencich/verilog-ethernet.git
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Add ADM-PCIE-9V3 25G example design
This commit is contained in:
Alex Forencich
parent
a031993b26
commit
1a28b0bf67
25
example/ADM_PCIE_9V3/fpga_25g/Makefile
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25
example/ADM_PCIE_9V3/fpga_25g/Makefile
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@ -0,0 +1,25 @@
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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24
example/ADM_PCIE_9V3/fpga_25g/README.md
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24
example/ADM_PCIE_9V3/fpga_25g/README.md
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# Verilog Ethernet ADM-PCIE-9V3 Example Design
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## Introduction
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This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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FPGA: xcvu3p-ffvc1517-2-i
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PHY: 25G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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## How to test
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Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run
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netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
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entered into netcat will be echoed back after pressing enter.
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118
example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk
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118
example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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tmpclean:
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-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean: tmpclean
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-rm -rf *.bit program.tcl
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distclean: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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%.xpr: Makefile $(XCI_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
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echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
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for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
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for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
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echo "exit" >> create_project.tcl
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vivado -mode batch -source create_project.tcl
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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echo "exit" >> run_synth.tcl
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vivado -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "exit" >> run_impl.tcl
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vivado -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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echo "exit" >> generate_bit.tcl
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vivado -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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176
example/ADM_PCIE_9V3/fpga_25g/fpga.xdc
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176
example/ADM_PCIE_9V3/fpga_25g/fpga.xdc
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@ -0,0 +1,176 @@
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# XDC constraints for the ADM-PCIE-9V3
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# part: xcvu3p-ffvc1517-2-i
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# 300 MHz system clock
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set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
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set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
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create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
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# LEDs
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set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
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set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
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set_property -dict {LOC AU23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_r}]
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set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[0]}]
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set_property -dict {LOC AJ23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[1]}]
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# Switches
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set_property -dict {LOC AV27 IOSTANDARD LVCMOS18} [get_ports {user_sw[0]}]
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set_property -dict {LOC AW27 IOSTANDARD LVCMOS18} [get_ports {user_sw[1]}]
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# GPIO
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#set_property -dict {LOC G30 IOSTANDARD LVCMOS18} [get_ports gpio_p[0]]
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#set_property -dict {LOC F30 IOSTANDARD LVCMOS18} [get_ports gpio_n[0]]
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#set_property -dict {LOC J31 IOSTANDARD LVCMOS18} [get_ports gpio_p[1]]
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#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
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# QSFP28 Interfaces
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set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
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#set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
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set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
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set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l]
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# 161.1328125 MHz MGT reference clock
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create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
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set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
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#set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
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set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
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set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l]
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# 161.1328125 MHz MGT reference clock
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create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
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set_property -dict {LOC B29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_reset_l]
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set_property -dict {LOC C29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_int_l]
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#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_i2c_scl]
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#set_property -dict {LOC A29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_i2c_sda]
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# PCIe Interface
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#set_property -dict {LOC J2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC J1 } [get_ports {pcie_rx_n[0]}] ;# MGTYTXP3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC H5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXN3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC H4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXP3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC L2 } [get_ports {pcie_rx_p[1]}] ;# MGTYTXN2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC L1 } [get_ports {pcie_rx_n[1]}] ;# MGTYTXP2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC K5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXN2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC K4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXP2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC N2 } [get_ports {pcie_rx_p[2]}] ;# MGTYTXN1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC N1 } [get_ports {pcie_rx_n[2]}] ;# MGTYTXP1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC M5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXN1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC M4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXP1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC R2 } [get_ports {pcie_rx_p[3]}] ;# MGTYTXN0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC R1 } [get_ports {pcie_rx_n[3]}] ;# MGTYTXP0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXN0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXP0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC U2 } [get_ports {pcie_rx_p[4]}] ;# MGTYTXN3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC U1 } [get_ports {pcie_rx_n[4]}] ;# MGTYTXP3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC T5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXN3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC T4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXP3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC W2 } [get_ports {pcie_rx_p[5]}] ;# MGTYTXN2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC W1 } [get_ports {pcie_rx_n[5]}] ;# MGTYTXP2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC V5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXN2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC V4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXP2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AA2 } [get_ports {pcie_rx_p[6]}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AA1 } [get_ports {pcie_rx_n[6]}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB5 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB4 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYTXN0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYTXP0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXN0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXP0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYTXN3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYTXP3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXN3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXP3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYTXN2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYTXP2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXN2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXP2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYTXN1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYTXP1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXN1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXP1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYTXN0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYTXP0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXN0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXP0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYTXN3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYTXP3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXN3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXP3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYTXN2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYTXP2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXN2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXP2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYTXN1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYTXP1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXN1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXP1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYTXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYTXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AA7 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226
|
||||
#set_property -dict {LOC AA6 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226
|
||||
#set_property -dict {LOC AJ7 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224
|
||||
#set_property -dict {LOC AJ6 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_224
|
||||
#set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_0]
|
||||
#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_1]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_clk}]
|
||||
#set_property -dict {LOC AB8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi0_dq[0]}]
|
||||
#set_property -dict {LOC AD8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi0_dq[1]}]
|
||||
#set_property -dict {LOC Y8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi0_dq[2]}]
|
||||
#set_property -dict {LOC AC8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi0_dq[3]}]
|
||||
#set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[0]}]
|
||||
#set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[1]}]
|
||||
#set_property -dict {LOC AF28 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[2]}]
|
||||
#set_property -dict {LOC AG28 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[3]}]
|
||||
69
example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
Normal file
69
example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
Normal file
@ -0,0 +1,69 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu3p-ffvc1517-2-i
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_reset.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
|
||||
SYN_FILES += lib/eth/rtl/arp_64.v
|
||||
SYN_FILES += lib/eth/rtl/arp_cache.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
|
||||
|
||||
# IP
|
||||
XCI_FILES += ip/gtwizard_ultrascale_0.xci
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "program_hw_devices [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -mode batch -source program.tcl
|
||||
|
||||
1411
example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.xci
Normal file
1411
example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
1
example/ADM_PCIE_9V3/fpga_25g/lib/eth
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/lib/eth
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../
|
||||
89
example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v
Normal file
89
example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||
*/
|
||||
module debounce_switch #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=3, // length of shift register
|
||||
parameter RATE=125000 // clock division factor
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [23:0] cnt_reg = 24'd0;
|
||||
|
||||
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||
|
||||
reg [WIDTH-1:0] state;
|
||||
|
||||
/*
|
||||
* The synchronized output is the state register
|
||||
*/
|
||||
assign out = state;
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
cnt_reg <= 0;
|
||||
state <= 0;
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (cnt_reg < RATE) begin
|
||||
cnt_reg <= cnt_reg + 24'd1;
|
||||
end else begin
|
||||
cnt_reg <= 24'd0;
|
||||
end
|
||||
|
||||
if (cnt_reg == 24'd0) begin
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||
end
|
||||
end
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
if (|debounce_reg[k] == 0) begin
|
||||
state[k] <= 0;
|
||||
end else if (&debounce_reg[k] == 1) begin
|
||||
state[k] <= 1;
|
||||
end else begin
|
||||
state[k] <= state[k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
904
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
Normal file
904
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
Normal file
@ -0,0 +1,904 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga (
|
||||
/*
|
||||
* Clock: 300MHz LVDS
|
||||
*/
|
||||
input wire clk_300mhz_p,
|
||||
input wire clk_300mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [1:0] user_led_g,
|
||||
output wire user_led_r,
|
||||
output wire [1:0] front_led,
|
||||
input wire [1:0] user_sw,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_modprs_l,
|
||||
output wire qsfp_0_sel_l,
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_modprs_l,
|
||||
output wire qsfp_1_sel_l,
|
||||
|
||||
output wire qsfp_reset_l,
|
||||
input wire qsfp_int_l
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_300mhz_ibufg;
|
||||
wire clk_125mhz_mmcm_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 156.25 MHz clock
|
||||
wire clk_156mhz_int;
|
||||
wire rst_156mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_300mhz_ibufg_inst (
|
||||
.O (clk_300mhz_ibufg),
|
||||
.I (clk_300mhz_p),
|
||||
.IB (clk_300mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
// 300 MHz in, 125 MHz out
|
||||
// PFD range: 10 MHz to 500 MHz
|
||||
// VCO range: 800 MHz to 1600 MHz
|
||||
// M = 10, D = 3 sets Fvco = 1000 MHz (in range)
|
||||
// Divide by 8 to get output frequency of 125 MHz
|
||||
MMCME3_BASE #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKOUT0_DIVIDE_F(8),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
.CLKFBOUT_MULT_F(10),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
.DIVCLK_DIVIDE(3),
|
||||
.REF_JITTER1(0.010),
|
||||
.CLKIN1_PERIOD(3.333),
|
||||
.STARTUP_WAIT("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
.CLKIN1(clk_300mhz_ibufg),
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.RST(mmcm_rst),
|
||||
.PWRDWN(1'b0),
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.CLKOUT6(),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.sync_reset_out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [1:0] user_sw_int;
|
||||
|
||||
debounce_switch #(
|
||||
.WIDTH(2),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({user_sw}),
|
||||
.out({user_sw_int})
|
||||
);
|
||||
|
||||
// XGMII 10G PHY
|
||||
assign qsfp_0_sel_l = 1'b0;
|
||||
|
||||
wire qsfp_0_tx_clk_0_int;
|
||||
wire qsfp_0_tx_rst_0_int;
|
||||
wire [63:0] qsfp_0_txd_0_int;
|
||||
wire [7:0] qsfp_0_txc_0_int;
|
||||
wire qsfp_0_rx_clk_0_int;
|
||||
wire qsfp_0_rx_rst_0_int;
|
||||
wire [63:0] qsfp_0_rxd_0_int;
|
||||
wire [7:0] qsfp_0_rxc_0_int;
|
||||
wire qsfp_0_tx_clk_1_int;
|
||||
wire qsfp_0_tx_rst_1_int;
|
||||
wire [63:0] qsfp_0_txd_1_int;
|
||||
wire [7:0] qsfp_0_txc_1_int;
|
||||
wire qsfp_0_rx_clk_1_int;
|
||||
wire qsfp_0_rx_rst_1_int;
|
||||
wire [63:0] qsfp_0_rxd_1_int;
|
||||
wire [7:0] qsfp_0_rxc_1_int;
|
||||
wire qsfp_0_tx_clk_2_int;
|
||||
wire qsfp_0_tx_rst_2_int;
|
||||
wire [63:0] qsfp_0_txd_2_int;
|
||||
wire [7:0] qsfp_0_txc_2_int;
|
||||
wire qsfp_0_rx_clk_2_int;
|
||||
wire qsfp_0_rx_rst_2_int;
|
||||
wire [63:0] qsfp_0_rxd_2_int;
|
||||
wire [7:0] qsfp_0_rxc_2_int;
|
||||
wire qsfp_0_tx_clk_3_int;
|
||||
wire qsfp_0_tx_rst_3_int;
|
||||
wire [63:0] qsfp_0_txd_3_int;
|
||||
wire [7:0] qsfp_0_txc_3_int;
|
||||
wire qsfp_0_rx_clk_3_int;
|
||||
wire qsfp_0_rx_rst_3_int;
|
||||
wire [63:0] qsfp_0_rxd_3_int;
|
||||
wire [7:0] qsfp_0_rxc_3_int;
|
||||
|
||||
assign qsfp_1_sel_l = 1'b0;
|
||||
|
||||
wire qsfp_1_tx_clk_0_int;
|
||||
wire qsfp_1_tx_rst_0_int;
|
||||
wire [63:0] qsfp_1_txd_0_int;
|
||||
wire [7:0] qsfp_1_txc_0_int;
|
||||
wire qsfp_1_rx_clk_0_int;
|
||||
wire qsfp_1_rx_rst_0_int;
|
||||
wire [63:0] qsfp_1_rxd_0_int;
|
||||
wire [7:0] qsfp_1_rxc_0_int;
|
||||
wire qsfp_1_tx_clk_1_int;
|
||||
wire qsfp_1_tx_rst_1_int;
|
||||
wire [63:0] qsfp_1_txd_1_int;
|
||||
wire [7:0] qsfp_1_txc_1_int;
|
||||
wire qsfp_1_rx_clk_1_int;
|
||||
wire qsfp_1_rx_rst_1_int;
|
||||
wire [63:0] qsfp_1_rxd_1_int;
|
||||
wire [7:0] qsfp_1_rxc_1_int;
|
||||
wire qsfp_1_tx_clk_2_int;
|
||||
wire qsfp_1_tx_rst_2_int;
|
||||
wire [63:0] qsfp_1_txd_2_int;
|
||||
wire [7:0] qsfp_1_txc_2_int;
|
||||
wire qsfp_1_rx_clk_2_int;
|
||||
wire qsfp_1_rx_rst_2_int;
|
||||
wire [63:0] qsfp_1_rxd_2_int;
|
||||
wire [7:0] qsfp_1_rxc_2_int;
|
||||
wire qsfp_1_tx_clk_3_int;
|
||||
wire qsfp_1_tx_rst_3_int;
|
||||
wire [63:0] qsfp_1_txd_3_int;
|
||||
wire [7:0] qsfp_1_txc_3_int;
|
||||
wire qsfp_1_rx_clk_3_int;
|
||||
wire qsfp_1_rx_rst_3_int;
|
||||
wire [63:0] qsfp_1_rxd_3_int;
|
||||
wire [7:0] qsfp_1_rxc_3_int;
|
||||
|
||||
assign qsfp_reset_l = 1'b1;
|
||||
|
||||
wire qsfp_0_rx_block_lock_0;
|
||||
wire qsfp_0_rx_block_lock_1;
|
||||
wire qsfp_0_rx_block_lock_2;
|
||||
wire qsfp_0_rx_block_lock_3;
|
||||
|
||||
wire qsfp_1_rx_block_lock_0;
|
||||
wire qsfp_1_rx_block_lock_1;
|
||||
wire qsfp_1_rx_block_lock_2;
|
||||
wire qsfp_1_rx_block_lock_3;
|
||||
|
||||
wire qsfp_0_mgt_refclk;
|
||||
wire qsfp_1_mgt_refclk;
|
||||
|
||||
wire [7:0] gt_txclkout;
|
||||
wire gt_txusrclk;
|
||||
|
||||
wire [7:0] gt_rxclkout;
|
||||
wire [7:0] gt_rxusrclk;
|
||||
|
||||
wire gt_reset_tx_done;
|
||||
wire gt_reset_rx_done;
|
||||
|
||||
wire [7:0] gt_txprgdivresetdone;
|
||||
wire [7:0] gt_txpmaresetdone;
|
||||
wire [7:0] gt_rxprgdivresetdone;
|
||||
wire [7:0] gt_rxpmaresetdone;
|
||||
|
||||
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
|
||||
wire gt_rx_reset = ~>_rxpmaresetdone;
|
||||
|
||||
reg gt_userclk_tx_active = 1'b0;
|
||||
reg [7:0] gt_userclk_rx_active = 1'b0;
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
|
||||
.I (qsfp_0_mgt_refclk_p),
|
||||
.IB (qsfp_0_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_0_mgt_refclk),
|
||||
.ODIV2 ()
|
||||
);
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
|
||||
.I (qsfp_1_mgt_refclk_p),
|
||||
.IB (qsfp_1_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_1_mgt_refclk),
|
||||
.ODIV2 ()
|
||||
);
|
||||
|
||||
|
||||
BUFG_GT bufg_gt_tx_usrclk_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_tx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_txclkout[0]),
|
||||
.O (gt_txusrclk)
|
||||
);
|
||||
|
||||
assign clk_156mhz_int = gt_txusrclk;
|
||||
|
||||
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
|
||||
if (gt_tx_reset) begin
|
||||
gt_userclk_tx_active <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_tx_active <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
|
||||
genvar n;
|
||||
|
||||
for (n = 0; n < 8; n = n + 1) begin
|
||||
|
||||
BUFG_GT bufg_gt_rx_usrclk_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_rx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_rxclkout[n]),
|
||||
.O (gt_rxusrclk[n])
|
||||
);
|
||||
|
||||
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
|
||||
if (gt_rx_reset) begin
|
||||
gt_userclk_rx_active[n] <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_rx_active[n] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_156mhz_inst (
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(~gt_reset_tx_done),
|
||||
.sync_reset_out(rst_156mhz_int)
|
||||
);
|
||||
|
||||
wire [5:0] qsfp_0_gt_txheader_0;
|
||||
wire [63:0] qsfp_0_gt_txdata_0;
|
||||
wire qsfp_0_gt_rxgearboxslip_0;
|
||||
wire [5:0] qsfp_0_gt_rxheader_0;
|
||||
wire [1:0] qsfp_0_gt_rxheadervalid_0;
|
||||
wire [63:0] qsfp_0_gt_rxdata_0;
|
||||
wire [1:0] qsfp_0_gt_rxdatavalid_0;
|
||||
|
||||
wire [5:0] qsfp_0_gt_txheader_1;
|
||||
wire [63:0] qsfp_0_gt_txdata_1;
|
||||
wire qsfp_0_gt_rxgearboxslip_1;
|
||||
wire [5:0] qsfp_0_gt_rxheader_1;
|
||||
wire [1:0] qsfp_0_gt_rxheadervalid_1;
|
||||
wire [63:0] qsfp_0_gt_rxdata_1;
|
||||
wire [1:0] qsfp_0_gt_rxdatavalid_1;
|
||||
|
||||
wire [5:0] qsfp_0_gt_txheader_2;
|
||||
wire [63:0] qsfp_0_gt_txdata_2;
|
||||
wire qsfp_0_gt_rxgearboxslip_2;
|
||||
wire [5:0] qsfp_0_gt_rxheader_2;
|
||||
wire [1:0] qsfp_0_gt_rxheadervalid_2;
|
||||
wire [63:0] qsfp_0_gt_rxdata_2;
|
||||
wire [1:0] qsfp_0_gt_rxdatavalid_2;
|
||||
|
||||
wire [5:0] qsfp_0_gt_txheader_3;
|
||||
wire [63:0] qsfp_0_gt_txdata_3;
|
||||
wire qsfp_0_gt_rxgearboxslip_3;
|
||||
wire [5:0] qsfp_0_gt_rxheader_3;
|
||||
wire [1:0] qsfp_0_gt_rxheadervalid_3;
|
||||
wire [63:0] qsfp_0_gt_rxdata_3;
|
||||
wire [1:0] qsfp_0_gt_rxdatavalid_3;
|
||||
|
||||
wire [5:0] qsfp_1_gt_txheader_0;
|
||||
wire [63:0] qsfp_1_gt_txdata_0;
|
||||
wire qsfp_1_gt_rxgearboxslip_0;
|
||||
wire [5:0] qsfp_1_gt_rxheader_0;
|
||||
wire [1:0] qsfp_1_gt_rxheadervalid_0;
|
||||
wire [63:0] qsfp_1_gt_rxdata_0;
|
||||
wire [1:0] qsfp_1_gt_rxdatavalid_0;
|
||||
|
||||
wire [5:0] qsfp_1_gt_txheader_1;
|
||||
wire [63:0] qsfp_1_gt_txdata_1;
|
||||
wire qsfp_1_gt_rxgearboxslip_1;
|
||||
wire [5:0] qsfp_1_gt_rxheader_1;
|
||||
wire [1:0] qsfp_1_gt_rxheadervalid_1;
|
||||
wire [63:0] qsfp_1_gt_rxdata_1;
|
||||
wire [1:0] qsfp_1_gt_rxdatavalid_1;
|
||||
|
||||
wire [5:0] qsfp_1_gt_txheader_2;
|
||||
wire [63:0] qsfp_1_gt_txdata_2;
|
||||
wire qsfp_1_gt_rxgearboxslip_2;
|
||||
wire [5:0] qsfp_1_gt_rxheader_2;
|
||||
wire [1:0] qsfp_1_gt_rxheadervalid_2;
|
||||
wire [63:0] qsfp_1_gt_rxdata_2;
|
||||
wire [1:0] qsfp_1_gt_rxdatavalid_2;
|
||||
|
||||
wire [5:0] qsfp_1_gt_txheader_3;
|
||||
wire [63:0] qsfp_1_gt_txdata_3;
|
||||
wire qsfp_1_gt_rxgearboxslip_3;
|
||||
wire [5:0] qsfp_1_gt_rxheader_3;
|
||||
wire [1:0] qsfp_1_gt_rxheadervalid_3;
|
||||
wire [63:0] qsfp_1_gt_rxdata_3;
|
||||
wire [1:0] qsfp_1_gt_rxdatavalid_3;
|
||||
|
||||
gtwizard_ultrascale_0
|
||||
qsfp_gty_inst (
|
||||
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
|
||||
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
|
||||
|
||||
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
|
||||
.gtwiz_reset_all_in(rst_125mhz_int),
|
||||
|
||||
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_tx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_rx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_cdr_stable_out(),
|
||||
|
||||
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
||||
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
||||
|
||||
.gtrefclk00_in({qsfp_0_mgt_refclk, qsfp_1_mgt_refclk}),
|
||||
|
||||
.qpll0outclk_out(),
|
||||
.qpll0outrefclk_out(),
|
||||
|
||||
.gtyrxn_in({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n, qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.gtyrxp_in({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p, qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
|
||||
.rxusrclk_in(gt_rxusrclk),
|
||||
.rxusrclk2_in(gt_rxusrclk),
|
||||
|
||||
.gtwiz_userdata_tx_in({qsfp_0_gt_txdata_3, qsfp_0_gt_txdata_2, qsfp_0_gt_txdata_1, qsfp_0_gt_txdata_0, qsfp_1_gt_txdata_3, qsfp_1_gt_txdata_2, qsfp_1_gt_txdata_1, qsfp_1_gt_txdata_0}),
|
||||
.txheader_in({qsfp_0_gt_txheader_3, qsfp_0_gt_txheader_2, qsfp_0_gt_txheader_1, qsfp_0_gt_txheader_0, qsfp_1_gt_txheader_3, qsfp_1_gt_txheader_2, qsfp_1_gt_txheader_1, qsfp_1_gt_txheader_0}),
|
||||
.txsequence_in({8{1'b0}}),
|
||||
|
||||
.txusrclk_in({8{gt_txusrclk}}),
|
||||
.txusrclk2_in({8{gt_txusrclk}}),
|
||||
|
||||
.gtpowergood_out(),
|
||||
|
||||
.gtytxn_out({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n, qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.gtytxp_out({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p, qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
|
||||
.rxgearboxslip_in({qsfp_0_gt_rxgearboxslip_3, qsfp_0_gt_rxgearboxslip_2, qsfp_0_gt_rxgearboxslip_1, qsfp_0_gt_rxgearboxslip_0, qsfp_1_gt_rxgearboxslip_3, qsfp_1_gt_rxgearboxslip_2, qsfp_1_gt_rxgearboxslip_1, qsfp_1_gt_rxgearboxslip_0}),
|
||||
.gtwiz_userdata_rx_out({qsfp_0_gt_rxdata_3, qsfp_0_gt_rxdata_2, qsfp_0_gt_rxdata_1, qsfp_0_gt_rxdata_0, qsfp_1_gt_rxdata_3, qsfp_1_gt_rxdata_2, qsfp_1_gt_rxdata_1, qsfp_1_gt_rxdata_0}),
|
||||
.rxdatavalid_out({qsfp_0_gt_rxdatavalid_3, qsfp_0_gt_rxdatavalid_2, qsfp_0_gt_rxdatavalid_1, qsfp_0_gt_rxdatavalid_0, qsfp_1_gt_rxdatavalid_3, qsfp_1_gt_rxdatavalid_2, qsfp_1_gt_rxdatavalid_1, qsfp_1_gt_rxdatavalid_0}),
|
||||
.rxheader_out({qsfp_0_gt_rxheader_3, qsfp_0_gt_rxheader_2, qsfp_0_gt_rxheader_1, qsfp_0_gt_rxheader_0, qsfp_1_gt_rxheader_3, qsfp_1_gt_rxheader_2, qsfp_1_gt_rxheader_1, qsfp_1_gt_rxheader_0}),
|
||||
.rxheadervalid_out({qsfp_0_gt_rxheadervalid_3, qsfp_0_gt_rxheadervalid_2, qsfp_0_gt_rxheadervalid_1, qsfp_0_gt_rxheadervalid_0, qsfp_1_gt_rxheadervalid_3, qsfp_1_gt_rxheadervalid_2, qsfp_1_gt_rxheadervalid_1, qsfp_1_gt_rxheadervalid_0}),
|
||||
.rxoutclk_out(gt_rxclkout),
|
||||
.rxpmaresetdone_out(gt_rxpmaresetdone),
|
||||
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
|
||||
.rxstartofseq_out(),
|
||||
|
||||
.txoutclk_out(gt_txclkout),
|
||||
.txpmaresetdone_out(gt_txpmaresetdone),
|
||||
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
||||
);
|
||||
|
||||
assign qsfp_0_tx_clk_0_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_0_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_0_int = gt_rxusrclk[4];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_rx_rst_0_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_0_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_rx_rst_0_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_0_phy_0_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_0_int),
|
||||
.tx_rst(qsfp_0_tx_rst_0_int),
|
||||
.rx_clk(qsfp_0_rx_clk_0_int),
|
||||
.rx_rst(qsfp_0_rx_rst_0_int),
|
||||
.xgmii_txd(qsfp_0_txd_0_int),
|
||||
.xgmii_txc(qsfp_0_txc_0_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_0_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_0_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_0),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_0),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_0),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_0),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_0),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_0),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_0_tx_clk_1_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_1_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_1_int = gt_rxusrclk[5];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_rx_rst_1_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_1_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_rx_rst_1_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_0_phy_1_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_1_int),
|
||||
.tx_rst(qsfp_0_tx_rst_1_int),
|
||||
.rx_clk(qsfp_0_rx_clk_1_int),
|
||||
.rx_rst(qsfp_0_rx_rst_1_int),
|
||||
.xgmii_txd(qsfp_0_txd_1_int),
|
||||
.xgmii_txc(qsfp_0_txc_1_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_1_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_1_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_1),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_1),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_1),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_1),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_1),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_1),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_0_tx_clk_2_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_2_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_2_int = gt_rxusrclk[6];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_rx_rst_2_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_2_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_rx_rst_2_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_0_phy_2_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_2_int),
|
||||
.tx_rst(qsfp_0_tx_rst_2_int),
|
||||
.rx_clk(qsfp_0_rx_clk_2_int),
|
||||
.rx_rst(qsfp_0_rx_rst_2_int),
|
||||
.xgmii_txd(qsfp_0_txd_2_int),
|
||||
.xgmii_txc(qsfp_0_txc_2_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_2_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_2_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_2),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_2),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_2),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_2),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_2),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_2),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_0_tx_clk_3_int = clk_156mhz_int;
|
||||
assign qsfp_0_tx_rst_3_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_0_rx_clk_3_int = gt_rxusrclk[7];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_0_rx_rst_3_reset_sync_inst (
|
||||
.clk(qsfp_0_rx_clk_3_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_0_rx_rst_3_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_0_phy_3_inst (
|
||||
.tx_clk(qsfp_0_tx_clk_3_int),
|
||||
.tx_rst(qsfp_0_tx_rst_3_int),
|
||||
.rx_clk(qsfp_0_rx_clk_3_int),
|
||||
.rx_rst(qsfp_0_rx_rst_3_int),
|
||||
.xgmii_txd(qsfp_0_txd_3_int),
|
||||
.xgmii_txc(qsfp_0_txc_3_int),
|
||||
.xgmii_rxd(qsfp_0_rxd_3_int),
|
||||
.xgmii_rxc(qsfp_0_rxc_3_int),
|
||||
.serdes_tx_data(qsfp_0_gt_txdata_3),
|
||||
.serdes_tx_hdr(qsfp_0_gt_txheader_3),
|
||||
.serdes_rx_data(qsfp_0_gt_rxdata_3),
|
||||
.serdes_rx_hdr(qsfp_0_gt_rxheader_3),
|
||||
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_3),
|
||||
.rx_block_lock(qsfp_0_rx_block_lock_3),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_1_tx_clk_0_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_0_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_0_int = gt_rxusrclk[0];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_rx_rst_0_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_0_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_rx_rst_0_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_1_phy_0_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_0_int),
|
||||
.tx_rst(qsfp_1_tx_rst_0_int),
|
||||
.rx_clk(qsfp_1_rx_clk_0_int),
|
||||
.rx_rst(qsfp_1_rx_rst_0_int),
|
||||
.xgmii_txd(qsfp_1_txd_0_int),
|
||||
.xgmii_txc(qsfp_1_txc_0_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_0_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_0_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_0),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_0),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_0),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_0),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_0),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_0),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_1_tx_clk_1_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_1_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_1_int = gt_rxusrclk[1];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_rx_rst_1_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_1_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_rx_rst_1_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_1_phy_1_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_1_int),
|
||||
.tx_rst(qsfp_1_tx_rst_1_int),
|
||||
.rx_clk(qsfp_1_rx_clk_1_int),
|
||||
.rx_rst(qsfp_1_rx_rst_1_int),
|
||||
.xgmii_txd(qsfp_1_txd_1_int),
|
||||
.xgmii_txc(qsfp_1_txc_1_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_1_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_1_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_1),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_1),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_1),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_1),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_1),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_1),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_1_tx_clk_2_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_2_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_2_int = gt_rxusrclk[2];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_rx_rst_2_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_2_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_rx_rst_2_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_1_phy_2_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_2_int),
|
||||
.tx_rst(qsfp_1_tx_rst_2_int),
|
||||
.rx_clk(qsfp_1_rx_clk_2_int),
|
||||
.rx_rst(qsfp_1_rx_rst_2_int),
|
||||
.xgmii_txd(qsfp_1_txd_2_int),
|
||||
.xgmii_txc(qsfp_1_txc_2_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_2_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_2_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_2),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_2),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_2),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_2),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_2),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_2),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign qsfp_1_tx_clk_3_int = clk_156mhz_int;
|
||||
assign qsfp_1_tx_rst_3_int = rst_156mhz_int;
|
||||
|
||||
assign qsfp_1_rx_clk_3_int = gt_rxusrclk[3];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_1_rx_rst_3_reset_sync_inst (
|
||||
.clk(qsfp_1_rx_clk_3_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(qsfp_1_rx_rst_3_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1),
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_1_phy_3_inst (
|
||||
.tx_clk(qsfp_1_tx_clk_3_int),
|
||||
.tx_rst(qsfp_1_tx_rst_3_int),
|
||||
.rx_clk(qsfp_1_rx_clk_3_int),
|
||||
.rx_rst(qsfp_1_rx_rst_3_int),
|
||||
.xgmii_txd(qsfp_1_txd_3_int),
|
||||
.xgmii_txc(qsfp_1_txc_3_int),
|
||||
.xgmii_rxd(qsfp_1_rxd_3_int),
|
||||
.xgmii_rxc(qsfp_1_rxc_3_int),
|
||||
.serdes_tx_data(qsfp_1_gt_txdata_3),
|
||||
.serdes_tx_hdr(qsfp_1_gt_txheader_3),
|
||||
.serdes_rx_data(qsfp_1_gt_rxdata_3),
|
||||
.serdes_rx_hdr(qsfp_1_gt_rxheader_3),
|
||||
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_3),
|
||||
.rx_block_lock(qsfp_1_rx_block_lock_3),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
//assign led = sw[0] ? {qsfp_1_rx_block_lock_4, qsfp_1_rx_block_lock_3, qsfp_1_rx_block_lock_2, qsfp_1_rx_block_lock_1, qsfp_0_rx_block_lock_4, qsfp_0_rx_block_lock_3, qsfp_0_rx_block_lock_2, qsfp_0_rx_block_lock_1} : led_int;
|
||||
assign front_led = {1'b0, qsfp_0_rx_block_lock_0};
|
||||
|
||||
fpga_core
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 156.25 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(rst_156mhz_int),
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.user_led_g(user_led_g),
|
||||
.user_led_r(user_led_r),
|
||||
//.front_led(front_led),
|
||||
.user_sw(user_sw_int),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
|
||||
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
|
||||
.qsfp_0_txd_0(qsfp_0_txd_0_int),
|
||||
.qsfp_0_txc_0(qsfp_0_txc_0_int),
|
||||
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
|
||||
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
|
||||
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
|
||||
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
|
||||
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
|
||||
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
|
||||
.qsfp_0_txd_1(qsfp_0_txd_1_int),
|
||||
.qsfp_0_txc_1(qsfp_0_txc_1_int),
|
||||
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
|
||||
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
|
||||
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
|
||||
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
|
||||
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
|
||||
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
|
||||
.qsfp_0_txd_2(qsfp_0_txd_2_int),
|
||||
.qsfp_0_txc_2(qsfp_0_txc_2_int),
|
||||
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
|
||||
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
|
||||
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
|
||||
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
|
||||
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
|
||||
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
|
||||
.qsfp_0_txd_3(qsfp_0_txd_3_int),
|
||||
.qsfp_0_txc_3(qsfp_0_txc_3_int),
|
||||
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
|
||||
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
|
||||
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
|
||||
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
|
||||
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
|
||||
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
|
||||
.qsfp_1_txd_0(qsfp_1_txd_0_int),
|
||||
.qsfp_1_txc_0(qsfp_1_txc_0_int),
|
||||
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
|
||||
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
|
||||
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
|
||||
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
|
||||
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
|
||||
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
|
||||
.qsfp_1_txd_1(qsfp_1_txd_1_int),
|
||||
.qsfp_1_txc_1(qsfp_1_txc_1_int),
|
||||
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
|
||||
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
|
||||
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
|
||||
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
|
||||
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
|
||||
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
|
||||
.qsfp_1_txd_2(qsfp_1_txd_2_int),
|
||||
.qsfp_1_txc_2(qsfp_1_txc_2_int),
|
||||
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
|
||||
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
|
||||
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
|
||||
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
|
||||
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
|
||||
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
|
||||
.qsfp_1_txd_3(qsfp_1_txd_3_int),
|
||||
.qsfp_1_txc_3(qsfp_1_txc_3_int),
|
||||
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
|
||||
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
|
||||
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
|
||||
.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
659
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
Normal file
659
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
Normal file
@ -0,0 +1,659 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter TARGET = "XILINX"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 156.25MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [1:0] user_led_g,
|
||||
output wire user_led_r,
|
||||
output wire [1:0] front_led,
|
||||
input wire [1:0] user_sw,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire qsfp_0_tx_clk_0,
|
||||
input wire qsfp_0_tx_rst_0,
|
||||
output wire [63:0] qsfp_0_txd_0,
|
||||
output wire [7:0] qsfp_0_txc_0,
|
||||
input wire qsfp_0_rx_clk_0,
|
||||
input wire qsfp_0_rx_rst_0,
|
||||
input wire [63:0] qsfp_0_rxd_0,
|
||||
input wire [7:0] qsfp_0_rxc_0,
|
||||
input wire qsfp_0_tx_clk_1,
|
||||
input wire qsfp_0_tx_rst_1,
|
||||
output wire [63:0] qsfp_0_txd_1,
|
||||
output wire [7:0] qsfp_0_txc_1,
|
||||
input wire qsfp_0_rx_clk_1,
|
||||
input wire qsfp_0_rx_rst_1,
|
||||
input wire [63:0] qsfp_0_rxd_1,
|
||||
input wire [7:0] qsfp_0_rxc_1,
|
||||
input wire qsfp_0_tx_clk_2,
|
||||
input wire qsfp_0_tx_rst_2,
|
||||
output wire [63:0] qsfp_0_txd_2,
|
||||
output wire [7:0] qsfp_0_txc_2,
|
||||
input wire qsfp_0_rx_clk_2,
|
||||
input wire qsfp_0_rx_rst_2,
|
||||
input wire [63:0] qsfp_0_rxd_2,
|
||||
input wire [7:0] qsfp_0_rxc_2,
|
||||
input wire qsfp_0_tx_clk_3,
|
||||
input wire qsfp_0_tx_rst_3,
|
||||
output wire [63:0] qsfp_0_txd_3,
|
||||
output wire [7:0] qsfp_0_txc_3,
|
||||
input wire qsfp_0_rx_clk_3,
|
||||
input wire qsfp_0_rx_rst_3,
|
||||
input wire [63:0] qsfp_0_rxd_3,
|
||||
input wire [7:0] qsfp_0_rxc_3,
|
||||
input wire qsfp_1_tx_clk_0,
|
||||
input wire qsfp_1_tx_rst_0,
|
||||
output wire [63:0] qsfp_1_txd_0,
|
||||
output wire [7:0] qsfp_1_txc_0,
|
||||
input wire qsfp_1_rx_clk_0,
|
||||
input wire qsfp_1_rx_rst_0,
|
||||
input wire [63:0] qsfp_1_rxd_0,
|
||||
input wire [7:0] qsfp_1_rxc_0,
|
||||
input wire qsfp_1_tx_clk_1,
|
||||
input wire qsfp_1_tx_rst_1,
|
||||
output wire [63:0] qsfp_1_txd_1,
|
||||
output wire [7:0] qsfp_1_txc_1,
|
||||
input wire qsfp_1_rx_clk_1,
|
||||
input wire qsfp_1_rx_rst_1,
|
||||
input wire [63:0] qsfp_1_rxd_1,
|
||||
input wire [7:0] qsfp_1_rxc_1,
|
||||
input wire qsfp_1_tx_clk_2,
|
||||
input wire qsfp_1_tx_rst_2,
|
||||
output wire [63:0] qsfp_1_txd_2,
|
||||
output wire [7:0] qsfp_1_txc_2,
|
||||
input wire qsfp_1_rx_clk_2,
|
||||
input wire qsfp_1_rx_rst_2,
|
||||
input wire [63:0] qsfp_1_rxd_2,
|
||||
input wire [7:0] qsfp_1_rxc_2,
|
||||
input wire qsfp_1_tx_clk_3,
|
||||
input wire qsfp_1_tx_rst_3,
|
||||
output wire [63:0] qsfp_1_txd_3,
|
||||
output wire [7:0] qsfp_1_txc_3,
|
||||
input wire qsfp_1_rx_clk_3,
|
||||
input wire qsfp_1_rx_rst_3,
|
||||
input wire [63:0] qsfp_1_rxd_3,
|
||||
input wire [7:0] qsfp_1_rxc_3
|
||||
);
|
||||
|
||||
// AXI between MAC and Ethernet modules
|
||||
wire [63:0] rx_axis_tdata;
|
||||
wire [7:0] rx_axis_tkeep;
|
||||
wire rx_axis_tvalid;
|
||||
wire rx_axis_tready;
|
||||
wire rx_axis_tlast;
|
||||
wire rx_axis_tuser;
|
||||
|
||||
wire [63:0] tx_axis_tdata;
|
||||
wire [7:0] tx_axis_tkeep;
|
||||
wire tx_axis_tvalid;
|
||||
wire tx_axis_tready;
|
||||
wire tx_axis_tlast;
|
||||
wire tx_axis_tuser;
|
||||
|
||||
// Ethernet frame between Ethernet modules and UDP stack
|
||||
wire rx_eth_hdr_ready;
|
||||
wire rx_eth_hdr_valid;
|
||||
wire [47:0] rx_eth_dest_mac;
|
||||
wire [47:0] rx_eth_src_mac;
|
||||
wire [15:0] rx_eth_type;
|
||||
wire [63:0] rx_eth_payload_axis_tdata;
|
||||
wire [7:0] rx_eth_payload_axis_tkeep;
|
||||
wire rx_eth_payload_axis_tvalid;
|
||||
wire rx_eth_payload_axis_tready;
|
||||
wire rx_eth_payload_axis_tlast;
|
||||
wire rx_eth_payload_axis_tuser;
|
||||
|
||||
wire tx_eth_hdr_ready;
|
||||
wire tx_eth_hdr_valid;
|
||||
wire [47:0] tx_eth_dest_mac;
|
||||
wire [47:0] tx_eth_src_mac;
|
||||
wire [15:0] tx_eth_type;
|
||||
wire [63:0] tx_eth_payload_axis_tdata;
|
||||
wire [7:0] tx_eth_payload_axis_tkeep;
|
||||
wire tx_eth_payload_axis_tvalid;
|
||||
wire tx_eth_payload_axis_tready;
|
||||
wire tx_eth_payload_axis_tlast;
|
||||
wire tx_eth_payload_axis_tuser;
|
||||
|
||||
// IP frame connections
|
||||
wire rx_ip_hdr_valid;
|
||||
wire rx_ip_hdr_ready;
|
||||
wire [47:0] rx_ip_eth_dest_mac;
|
||||
wire [47:0] rx_ip_eth_src_mac;
|
||||
wire [15:0] rx_ip_eth_type;
|
||||
wire [3:0] rx_ip_version;
|
||||
wire [3:0] rx_ip_ihl;
|
||||
wire [5:0] rx_ip_dscp;
|
||||
wire [1:0] rx_ip_ecn;
|
||||
wire [15:0] rx_ip_length;
|
||||
wire [15:0] rx_ip_identification;
|
||||
wire [2:0] rx_ip_flags;
|
||||
wire [12:0] rx_ip_fragment_offset;
|
||||
wire [7:0] rx_ip_ttl;
|
||||
wire [7:0] rx_ip_protocol;
|
||||
wire [15:0] rx_ip_header_checksum;
|
||||
wire [31:0] rx_ip_source_ip;
|
||||
wire [31:0] rx_ip_dest_ip;
|
||||
wire [63:0] rx_ip_payload_axis_tdata;
|
||||
wire [7:0] rx_ip_payload_axis_tkeep;
|
||||
wire rx_ip_payload_axis_tvalid;
|
||||
wire rx_ip_payload_axis_tready;
|
||||
wire rx_ip_payload_axis_tlast;
|
||||
wire rx_ip_payload_axis_tuser;
|
||||
|
||||
wire tx_ip_hdr_valid;
|
||||
wire tx_ip_hdr_ready;
|
||||
wire [5:0] tx_ip_dscp;
|
||||
wire [1:0] tx_ip_ecn;
|
||||
wire [15:0] tx_ip_length;
|
||||
wire [7:0] tx_ip_ttl;
|
||||
wire [7:0] tx_ip_protocol;
|
||||
wire [31:0] tx_ip_source_ip;
|
||||
wire [31:0] tx_ip_dest_ip;
|
||||
wire [63:0] tx_ip_payload_axis_tdata;
|
||||
wire [7:0] tx_ip_payload_axis_tkeep;
|
||||
wire tx_ip_payload_axis_tvalid;
|
||||
wire tx_ip_payload_axis_tready;
|
||||
wire tx_ip_payload_axis_tlast;
|
||||
wire tx_ip_payload_axis_tuser;
|
||||
|
||||
// UDP frame connections
|
||||
wire rx_udp_hdr_valid;
|
||||
wire rx_udp_hdr_ready;
|
||||
wire [47:0] rx_udp_eth_dest_mac;
|
||||
wire [47:0] rx_udp_eth_src_mac;
|
||||
wire [15:0] rx_udp_eth_type;
|
||||
wire [3:0] rx_udp_ip_version;
|
||||
wire [3:0] rx_udp_ip_ihl;
|
||||
wire [5:0] rx_udp_ip_dscp;
|
||||
wire [1:0] rx_udp_ip_ecn;
|
||||
wire [15:0] rx_udp_ip_length;
|
||||
wire [15:0] rx_udp_ip_identification;
|
||||
wire [2:0] rx_udp_ip_flags;
|
||||
wire [12:0] rx_udp_ip_fragment_offset;
|
||||
wire [7:0] rx_udp_ip_ttl;
|
||||
wire [7:0] rx_udp_ip_protocol;
|
||||
wire [15:0] rx_udp_ip_header_checksum;
|
||||
wire [31:0] rx_udp_ip_source_ip;
|
||||
wire [31:0] rx_udp_ip_dest_ip;
|
||||
wire [15:0] rx_udp_source_port;
|
||||
wire [15:0] rx_udp_dest_port;
|
||||
wire [15:0] rx_udp_length;
|
||||
wire [15:0] rx_udp_checksum;
|
||||
wire [63:0] rx_udp_payload_axis_tdata;
|
||||
wire [7:0] rx_udp_payload_axis_tkeep;
|
||||
wire rx_udp_payload_axis_tvalid;
|
||||
wire rx_udp_payload_axis_tready;
|
||||
wire rx_udp_payload_axis_tlast;
|
||||
wire rx_udp_payload_axis_tuser;
|
||||
|
||||
wire tx_udp_hdr_valid;
|
||||
wire tx_udp_hdr_ready;
|
||||
wire [5:0] tx_udp_ip_dscp;
|
||||
wire [1:0] tx_udp_ip_ecn;
|
||||
wire [7:0] tx_udp_ip_ttl;
|
||||
wire [31:0] tx_udp_ip_source_ip;
|
||||
wire [31:0] tx_udp_ip_dest_ip;
|
||||
wire [15:0] tx_udp_source_port;
|
||||
wire [15:0] tx_udp_dest_port;
|
||||
wire [15:0] tx_udp_length;
|
||||
wire [15:0] tx_udp_checksum;
|
||||
wire [63:0] tx_udp_payload_axis_tdata;
|
||||
wire [7:0] tx_udp_payload_axis_tkeep;
|
||||
wire tx_udp_payload_axis_tvalid;
|
||||
wire tx_udp_payload_axis_tready;
|
||||
wire tx_udp_payload_axis_tlast;
|
||||
wire tx_udp_payload_axis_tuser;
|
||||
|
||||
wire [63:0] rx_fifo_udp_payload_axis_tdata;
|
||||
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
|
||||
wire rx_fifo_udp_payload_axis_tvalid;
|
||||
wire rx_fifo_udp_payload_axis_tready;
|
||||
wire rx_fifo_udp_payload_axis_tlast;
|
||||
wire rx_fifo_udp_payload_axis_tuser;
|
||||
|
||||
wire [63:0] tx_fifo_udp_payload_axis_tdata;
|
||||
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
|
||||
wire tx_fifo_udp_payload_axis_tvalid;
|
||||
wire tx_fifo_udp_payload_axis_tready;
|
||||
wire tx_fifo_udp_payload_axis_tlast;
|
||||
wire tx_fifo_udp_payload_axis_tuser;
|
||||
|
||||
// Configuration
|
||||
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
|
||||
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
|
||||
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
|
||||
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
|
||||
|
||||
// IP ports not used
|
||||
assign rx_ip_hdr_ready = 1;
|
||||
assign rx_ip_payload_axis_tready = 1;
|
||||
|
||||
assign tx_ip_hdr_valid = 0;
|
||||
assign tx_ip_dscp = 0;
|
||||
assign tx_ip_ecn = 0;
|
||||
assign tx_ip_length = 0;
|
||||
assign tx_ip_ttl = 0;
|
||||
assign tx_ip_protocol = 0;
|
||||
assign tx_ip_source_ip = 0;
|
||||
assign tx_ip_dest_ip = 0;
|
||||
assign tx_ip_payload_axis_tdata = 0;
|
||||
assign tx_ip_payload_axis_tkeep = 0;
|
||||
assign tx_ip_payload_axis_tvalid = 0;
|
||||
assign tx_ip_payload_axis_tlast = 0;
|
||||
assign tx_ip_payload_axis_tuser = 0;
|
||||
|
||||
// Loop back UDP
|
||||
wire match_cond = rx_udp_dest_port == 1234;
|
||||
wire no_match = !match_cond;
|
||||
|
||||
reg match_cond_reg = 0;
|
||||
reg no_match_reg = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
match_cond_reg <= 0;
|
||||
no_match_reg <= 0;
|
||||
end else begin
|
||||
if (rx_udp_payload_axis_tvalid) begin
|
||||
if ((!match_cond_reg && !no_match_reg) ||
|
||||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
|
||||
match_cond_reg <= match_cond;
|
||||
no_match_reg <= no_match;
|
||||
end
|
||||
end else begin
|
||||
match_cond_reg <= 0;
|
||||
no_match_reg <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
|
||||
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
|
||||
assign tx_udp_ip_dscp = 0;
|
||||
assign tx_udp_ip_ecn = 0;
|
||||
assign tx_udp_ip_ttl = 64;
|
||||
assign tx_udp_ip_source_ip = local_ip;
|
||||
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
|
||||
assign tx_udp_source_port = rx_udp_dest_port;
|
||||
assign tx_udp_dest_port = rx_udp_source_port;
|
||||
assign tx_udp_length = rx_udp_length;
|
||||
assign tx_udp_checksum = 0;
|
||||
|
||||
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
|
||||
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
|
||||
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
|
||||
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
|
||||
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
|
||||
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
|
||||
|
||||
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
|
||||
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
|
||||
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
|
||||
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
|
||||
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
|
||||
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
|
||||
|
||||
// Place first payload byte onto LEDs
|
||||
reg valid_last = 0;
|
||||
reg [7:0] led_reg = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
led_reg <= 0;
|
||||
end else begin
|
||||
valid_last <= tx_udp_payload_axis_tvalid;
|
||||
if (tx_udp_payload_axis_tvalid && !valid_last) begin
|
||||
led_reg <= tx_udp_payload_axis_tdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign user_led_g = ~led_reg[1:0];
|
||||
assign user_led_r = 1'b1;
|
||||
assign front_led = 2'b00;
|
||||
|
||||
assign phy_reset_n = !rst;
|
||||
|
||||
assign qsfp_0_txd_1 = 64'h0707070707070707;
|
||||
assign qsfp_0_txc_1 = 8'hff;
|
||||
assign qsfp_0_txd_2 = 64'h0707070707070707;
|
||||
assign qsfp_0_txc_2 = 8'hff;
|
||||
assign qsfp_0_txd_3 = 64'h0707070707070707;
|
||||
assign qsfp_0_txc_3 = 8'hff;
|
||||
|
||||
assign qsfp_1_txd_0 = 64'h0707070707070707;
|
||||
assign qsfp_1_txc_0 = 8'hff;
|
||||
assign qsfp_1_txd_1 = 64'h0707070707070707;
|
||||
assign qsfp_1_txc_1 = 8'hff;
|
||||
assign qsfp_1_txd_2 = 64'h0707070707070707;
|
||||
assign qsfp_1_txc_2 = 8'hff;
|
||||
assign qsfp_1_txd_3 = 64'h0707070707070707;
|
||||
assign qsfp_1_txc_3 = 8'hff;
|
||||
|
||||
eth_mac_10g_fifo #(
|
||||
.ENABLE_PADDING(1),
|
||||
.ENABLE_DIC(1),
|
||||
.MIN_FRAME_LENGTH(64),
|
||||
.TX_FIFO_ADDR_WIDTH(9),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_ADDR_WIDTH(9),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_10g_fifo_inst (
|
||||
.rx_clk(qsfp_0_rx_clk_0),
|
||||
.rx_rst(qsfp_0_rx_rst_0),
|
||||
.tx_clk(qsfp_0_tx_clk_0),
|
||||
.tx_rst(qsfp_0_tx_rst_0),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
.tx_axis_tdata(tx_axis_tdata),
|
||||
.tx_axis_tkeep(tx_axis_tkeep),
|
||||
.tx_axis_tvalid(tx_axis_tvalid),
|
||||
.tx_axis_tready(tx_axis_tready),
|
||||
.tx_axis_tlast(tx_axis_tlast),
|
||||
.tx_axis_tuser(tx_axis_tuser),
|
||||
|
||||
.rx_axis_tdata(rx_axis_tdata),
|
||||
.rx_axis_tkeep(rx_axis_tkeep),
|
||||
.rx_axis_tvalid(rx_axis_tvalid),
|
||||
.rx_axis_tready(rx_axis_tready),
|
||||
.rx_axis_tlast(rx_axis_tlast),
|
||||
.rx_axis_tuser(rx_axis_tuser),
|
||||
|
||||
.xgmii_rxd(qsfp_0_rxd_0),
|
||||
.xgmii_rxc(qsfp_0_rxc_0),
|
||||
.xgmii_txd(qsfp_0_txd_0),
|
||||
.xgmii_txc(qsfp_0_txc_0),
|
||||
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
.ifg_delay(8'd12)
|
||||
);
|
||||
|
||||
eth_axis_rx_64
|
||||
eth_axis_rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.s_axis_tdata(rx_axis_tdata),
|
||||
.s_axis_tkeep(rx_axis_tkeep),
|
||||
.s_axis_tvalid(rx_axis_tvalid),
|
||||
.s_axis_tready(rx_axis_tready),
|
||||
.s_axis_tlast(rx_axis_tlast),
|
||||
.s_axis_tuser(rx_axis_tuser),
|
||||
// Ethernet frame output
|
||||
.m_eth_hdr_valid(rx_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(rx_eth_hdr_ready),
|
||||
.m_eth_dest_mac(rx_eth_dest_mac),
|
||||
.m_eth_src_mac(rx_eth_src_mac),
|
||||
.m_eth_type(rx_eth_type),
|
||||
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
|
||||
// Status signals
|
||||
.busy(),
|
||||
.error_header_early_termination()
|
||||
);
|
||||
|
||||
eth_axis_tx_64
|
||||
eth_axis_tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame input
|
||||
.s_eth_hdr_valid(tx_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(tx_eth_hdr_ready),
|
||||
.s_eth_dest_mac(tx_eth_dest_mac),
|
||||
.s_eth_src_mac(tx_eth_src_mac),
|
||||
.s_eth_type(tx_eth_type),
|
||||
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
|
||||
// AXI output
|
||||
.m_axis_tdata(tx_axis_tdata),
|
||||
.m_axis_tkeep(tx_axis_tkeep),
|
||||
.m_axis_tvalid(tx_axis_tvalid),
|
||||
.m_axis_tready(tx_axis_tready),
|
||||
.m_axis_tlast(tx_axis_tlast),
|
||||
.m_axis_tuser(tx_axis_tuser),
|
||||
// Status signals
|
||||
.busy()
|
||||
);
|
||||
|
||||
udp_complete_64
|
||||
udp_complete_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame input
|
||||
.s_eth_hdr_valid(rx_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(rx_eth_hdr_ready),
|
||||
.s_eth_dest_mac(rx_eth_dest_mac),
|
||||
.s_eth_src_mac(rx_eth_src_mac),
|
||||
.s_eth_type(rx_eth_type),
|
||||
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
|
||||
// Ethernet frame output
|
||||
.m_eth_hdr_valid(tx_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(tx_eth_hdr_ready),
|
||||
.m_eth_dest_mac(tx_eth_dest_mac),
|
||||
.m_eth_src_mac(tx_eth_src_mac),
|
||||
.m_eth_type(tx_eth_type),
|
||||
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
|
||||
// IP frame input
|
||||
.s_ip_hdr_valid(tx_ip_hdr_valid),
|
||||
.s_ip_hdr_ready(tx_ip_hdr_ready),
|
||||
.s_ip_dscp(tx_ip_dscp),
|
||||
.s_ip_ecn(tx_ip_ecn),
|
||||
.s_ip_length(tx_ip_length),
|
||||
.s_ip_ttl(tx_ip_ttl),
|
||||
.s_ip_protocol(tx_ip_protocol),
|
||||
.s_ip_source_ip(tx_ip_source_ip),
|
||||
.s_ip_dest_ip(tx_ip_dest_ip),
|
||||
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
|
||||
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
|
||||
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
|
||||
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
|
||||
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
|
||||
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
|
||||
// IP frame output
|
||||
.m_ip_hdr_valid(rx_ip_hdr_valid),
|
||||
.m_ip_hdr_ready(rx_ip_hdr_ready),
|
||||
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
|
||||
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
|
||||
.m_ip_eth_type(rx_ip_eth_type),
|
||||
.m_ip_version(rx_ip_version),
|
||||
.m_ip_ihl(rx_ip_ihl),
|
||||
.m_ip_dscp(rx_ip_dscp),
|
||||
.m_ip_ecn(rx_ip_ecn),
|
||||
.m_ip_length(rx_ip_length),
|
||||
.m_ip_identification(rx_ip_identification),
|
||||
.m_ip_flags(rx_ip_flags),
|
||||
.m_ip_fragment_offset(rx_ip_fragment_offset),
|
||||
.m_ip_ttl(rx_ip_ttl),
|
||||
.m_ip_protocol(rx_ip_protocol),
|
||||
.m_ip_header_checksum(rx_ip_header_checksum),
|
||||
.m_ip_source_ip(rx_ip_source_ip),
|
||||
.m_ip_dest_ip(rx_ip_dest_ip),
|
||||
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
|
||||
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
|
||||
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
|
||||
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
|
||||
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
|
||||
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
|
||||
// UDP frame input
|
||||
.s_udp_hdr_valid(tx_udp_hdr_valid),
|
||||
.s_udp_hdr_ready(tx_udp_hdr_ready),
|
||||
.s_udp_ip_dscp(tx_udp_ip_dscp),
|
||||
.s_udp_ip_ecn(tx_udp_ip_ecn),
|
||||
.s_udp_ip_ttl(tx_udp_ip_ttl),
|
||||
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
|
||||
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
|
||||
.s_udp_source_port(tx_udp_source_port),
|
||||
.s_udp_dest_port(tx_udp_dest_port),
|
||||
.s_udp_length(tx_udp_length),
|
||||
.s_udp_checksum(tx_udp_checksum),
|
||||
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
|
||||
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
|
||||
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
|
||||
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
|
||||
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
|
||||
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
|
||||
// UDP frame output
|
||||
.m_udp_hdr_valid(rx_udp_hdr_valid),
|
||||
.m_udp_hdr_ready(rx_udp_hdr_ready),
|
||||
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
|
||||
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
|
||||
.m_udp_eth_type(rx_udp_eth_type),
|
||||
.m_udp_ip_version(rx_udp_ip_version),
|
||||
.m_udp_ip_ihl(rx_udp_ip_ihl),
|
||||
.m_udp_ip_dscp(rx_udp_ip_dscp),
|
||||
.m_udp_ip_ecn(rx_udp_ip_ecn),
|
||||
.m_udp_ip_length(rx_udp_ip_length),
|
||||
.m_udp_ip_identification(rx_udp_ip_identification),
|
||||
.m_udp_ip_flags(rx_udp_ip_flags),
|
||||
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
|
||||
.m_udp_ip_ttl(rx_udp_ip_ttl),
|
||||
.m_udp_ip_protocol(rx_udp_ip_protocol),
|
||||
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
|
||||
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
|
||||
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
|
||||
.m_udp_source_port(rx_udp_source_port),
|
||||
.m_udp_dest_port(rx_udp_dest_port),
|
||||
.m_udp_length(rx_udp_length),
|
||||
.m_udp_checksum(rx_udp_checksum),
|
||||
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
|
||||
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
|
||||
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
|
||||
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
|
||||
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
|
||||
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
|
||||
// Status signals
|
||||
.ip_rx_busy(),
|
||||
.ip_tx_busy(),
|
||||
.udp_rx_busy(),
|
||||
.udp_tx_busy(),
|
||||
.ip_rx_error_header_early_termination(),
|
||||
.ip_rx_error_payload_early_termination(),
|
||||
.ip_rx_error_invalid_header(),
|
||||
.ip_rx_error_invalid_checksum(),
|
||||
.ip_tx_error_payload_early_termination(),
|
||||
.ip_tx_error_arp_failed(),
|
||||
.udp_rx_error_header_early_termination(),
|
||||
.udp_rx_error_payload_early_termination(),
|
||||
.udp_tx_error_payload_early_termination(),
|
||||
// Configuration
|
||||
.local_mac(local_mac),
|
||||
.local_ip(local_ip),
|
||||
.gateway_ip(gateway_ip),
|
||||
.subnet_mask(subnet_mask),
|
||||
.clear_arp_cache(1'b0)
|
||||
);
|
||||
|
||||
axis_fifo #(
|
||||
.ADDR_WIDTH(10),
|
||||
.DATA_WIDTH(64),
|
||||
.KEEP_ENABLE(1),
|
||||
.KEEP_WIDTH(8),
|
||||
.ID_ENABLE(0),
|
||||
.DEST_ENABLE(0),
|
||||
.USER_ENABLE(1),
|
||||
.USER_WIDTH(1),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
udp_payload_fifo (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// AXI input
|
||||
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
|
||||
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
|
||||
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
|
||||
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
|
||||
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
|
||||
.s_axis_tid(0),
|
||||
.s_axis_tdest(0),
|
||||
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
|
||||
|
||||
// AXI output
|
||||
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
|
||||
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
|
||||
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
|
||||
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
|
||||
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
|
||||
|
||||
// Status
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
endmodule
|
||||
52
example/ADM_PCIE_9V3/fpga_25g/rtl/sync_reset.v
Normal file
52
example/ADM_PCIE_9V3/fpga_25g/rtl/sync_reset.v
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an active-high asynchronous reset signal to a given clock by
|
||||
* using a pipeline of N registers.
|
||||
*/
|
||||
module sync_reset #(
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
output wire sync_reset_out
|
||||
);
|
||||
|
||||
reg [N-1:0] sync_reg = {N{1'b1}};
|
||||
|
||||
assign sync_reset_out = sync_reg[N-1];
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst)
|
||||
sync_reg <= {N{1'b1}};
|
||||
else
|
||||
sync_reg <= {sync_reg[N-2:0], 1'b0};
|
||||
end
|
||||
|
||||
endmodule
|
||||
58
example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v
Normal file
58
example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
example/ADM_PCIE_9V3/fpga_25g/tb/arp_ep.py
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/tb/arp_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/arp_ep.py
|
||||
1
example/ADM_PCIE_9V3/fpga_25g/tb/axis_ep.py
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/axis_ep.py
|
||||
1
example/ADM_PCIE_9V3/fpga_25g/tb/eth_ep.py
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/tb/eth_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/eth_ep.py
|
||||
1
example/ADM_PCIE_9V3/fpga_25g/tb/ip_ep.py
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/tb/ip_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/ip_ep.py
|
||||
462
example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py
Executable file
462
example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py
Executable file
@ -0,0 +1,462 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2016-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
import eth_ep
|
||||
import arp_ep
|
||||
import udp_ep
|
||||
import xgmii_ep
|
||||
|
||||
module = 'fpga_core'
|
||||
testbench = 'test_%s' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/lfsr.v")
|
||||
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_complete_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_checksum_gen_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_ip_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_ip_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_complete_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_arb_mux.v")
|
||||
srcs.append("../lib/eth/rtl/arp_64.v")
|
||||
srcs.append("../lib/eth/rtl/arp_cache.v")
|
||||
srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/eth_arb_mux.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
user_sw = Signal(intbv(0)[2:])
|
||||
qsfp_0_tx_clk_0 = Signal(bool(0))
|
||||
qsfp_0_tx_rst_0 = Signal(bool(0))
|
||||
qsfp_0_rx_clk_0 = Signal(bool(0))
|
||||
qsfp_0_rx_rst_0 = Signal(bool(0))
|
||||
qsfp_0_rxd_0 = Signal(intbv(0)[64:])
|
||||
qsfp_0_rxc_0 = Signal(intbv(0)[8:])
|
||||
qsfp_0_tx_clk_1 = Signal(bool(0))
|
||||
qsfp_0_tx_rst_1 = Signal(bool(0))
|
||||
qsfp_0_rx_clk_1 = Signal(bool(0))
|
||||
qsfp_0_rx_rst_1 = Signal(bool(0))
|
||||
qsfp_0_rxd_1 = Signal(intbv(0)[64:])
|
||||
qsfp_0_rxc_1 = Signal(intbv(0)[8:])
|
||||
qsfp_0_tx_clk_2 = Signal(bool(0))
|
||||
qsfp_0_tx_rst_2 = Signal(bool(0))
|
||||
qsfp_0_rx_clk_2 = Signal(bool(0))
|
||||
qsfp_0_rx_rst_2 = Signal(bool(0))
|
||||
qsfp_0_rxd_2 = Signal(intbv(0)[64:])
|
||||
qsfp_0_rxc_2 = Signal(intbv(0)[8:])
|
||||
qsfp_0_tx_clk_3 = Signal(bool(0))
|
||||
qsfp_0_tx_rst_3 = Signal(bool(0))
|
||||
qsfp_0_rx_clk_3 = Signal(bool(0))
|
||||
qsfp_0_rx_rst_3 = Signal(bool(0))
|
||||
qsfp_0_rxd_3 = Signal(intbv(0)[64:])
|
||||
qsfp_0_rxc_3 = Signal(intbv(0)[8:])
|
||||
qsfp_1_tx_clk_0 = Signal(bool(0))
|
||||
qsfp_1_tx_rst_0 = Signal(bool(0))
|
||||
qsfp_1_rx_clk_0 = Signal(bool(0))
|
||||
qsfp_1_rx_rst_0 = Signal(bool(0))
|
||||
qsfp_1_rxd_0 = Signal(intbv(0)[64:])
|
||||
qsfp_1_rxc_0 = Signal(intbv(0)[8:])
|
||||
qsfp_1_tx_clk_1 = Signal(bool(0))
|
||||
qsfp_1_tx_rst_1 = Signal(bool(0))
|
||||
qsfp_1_rx_clk_1 = Signal(bool(0))
|
||||
qsfp_1_rx_rst_1 = Signal(bool(0))
|
||||
qsfp_1_rxd_1 = Signal(intbv(0)[64:])
|
||||
qsfp_1_rxc_1 = Signal(intbv(0)[8:])
|
||||
qsfp_1_tx_clk_2 = Signal(bool(0))
|
||||
qsfp_1_tx_rst_2 = Signal(bool(0))
|
||||
qsfp_1_rx_clk_2 = Signal(bool(0))
|
||||
qsfp_1_rx_rst_2 = Signal(bool(0))
|
||||
qsfp_1_rxd_2 = Signal(intbv(0)[64:])
|
||||
qsfp_1_rxc_2 = Signal(intbv(0)[8:])
|
||||
qsfp_1_tx_clk_3 = Signal(bool(0))
|
||||
qsfp_1_tx_rst_3 = Signal(bool(0))
|
||||
qsfp_1_rx_clk_3 = Signal(bool(0))
|
||||
qsfp_1_rx_rst_3 = Signal(bool(0))
|
||||
qsfp_1_rxd_3 = Signal(intbv(0)[64:])
|
||||
qsfp_1_rxc_3 = Signal(intbv(0)[8:])
|
||||
|
||||
# Outputs
|
||||
user_led_g = Signal(intbv(0)[2:])
|
||||
user_led_r = Signal(bool(0))
|
||||
front_led = Signal(intbv(0)[2:])
|
||||
qsfp_0_txd_0 = Signal(intbv(0)[64:])
|
||||
qsfp_0_txc_0 = Signal(intbv(0)[8:])
|
||||
qsfp_0_txd_1 = Signal(intbv(0)[64:])
|
||||
qsfp_0_txc_1 = Signal(intbv(0)[8:])
|
||||
qsfp_0_txd_2 = Signal(intbv(0)[64:])
|
||||
qsfp_0_txc_2 = Signal(intbv(0)[8:])
|
||||
qsfp_0_txd_3 = Signal(intbv(0)[64:])
|
||||
qsfp_0_txc_3 = Signal(intbv(0)[8:])
|
||||
qsfp_1_txd_0 = Signal(intbv(0)[64:])
|
||||
qsfp_1_txc_0 = Signal(intbv(0)[8:])
|
||||
qsfp_1_txd_1 = Signal(intbv(0)[64:])
|
||||
qsfp_1_txc_1 = Signal(intbv(0)[8:])
|
||||
qsfp_1_txd_2 = Signal(intbv(0)[64:])
|
||||
qsfp_1_txc_2 = Signal(intbv(0)[8:])
|
||||
qsfp_1_txd_3 = Signal(intbv(0)[64:])
|
||||
qsfp_1_txc_3 = Signal(intbv(0)[8:])
|
||||
|
||||
# sources and sinks
|
||||
qsfp_0_0_source = xgmii_ep.XGMIISource()
|
||||
qsfp_0_0_source_logic = qsfp_0_0_source.create_logic(qsfp_0_rx_clk_0, qsfp_0_rx_rst_0, txd=qsfp_0_rxd_0, txc=qsfp_0_rxc_0, name='qsfp_0_0_source')
|
||||
|
||||
qsfp_0_0_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_0_0_sink_logic = qsfp_0_0_sink.create_logic(qsfp_0_tx_clk_0, qsfp_0_tx_rst_0, rxd=qsfp_0_txd_0, rxc=qsfp_0_txc_0, name='qsfp_0_0_sink')
|
||||
|
||||
qsfp_0_1_source = xgmii_ep.XGMIISource()
|
||||
qsfp_0_1_source_logic = qsfp_0_1_source.create_logic(qsfp_0_rx_clk_1, qsfp_0_rx_rst_1, txd=qsfp_0_rxd_1, txc=qsfp_0_rxc_1, name='qsfp_0_1_source')
|
||||
|
||||
qsfp_0_1_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_0_1_sink_logic = qsfp_0_1_sink.create_logic(qsfp_0_tx_clk_1, qsfp_0_tx_rst_1, rxd=qsfp_0_txd_1, rxc=qsfp_0_txc_1, name='qsfp_0_1_sink')
|
||||
|
||||
qsfp_0_2_source = xgmii_ep.XGMIISource()
|
||||
qsfp_0_2_source_logic = qsfp_0_2_source.create_logic(qsfp_0_rx_clk_2, qsfp_0_rx_rst_2, txd=qsfp_0_rxd_2, txc=qsfp_0_rxc_2, name='qsfp_0_2_source')
|
||||
|
||||
qsfp_0_2_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_0_2_sink_logic = qsfp_0_2_sink.create_logic(qsfp_0_tx_clk_2, qsfp_0_tx_rst_2, rxd=qsfp_0_txd_2, rxc=qsfp_0_txc_2, name='qsfp_0_2_sink')
|
||||
|
||||
qsfp_0_3_source = xgmii_ep.XGMIISource()
|
||||
qsfp_0_3_source_logic = qsfp_0_3_source.create_logic(qsfp_0_rx_clk_3, qsfp_0_rx_rst_3, txd=qsfp_0_rxd_3, txc=qsfp_0_rxc_3, name='qsfp_0_3_source')
|
||||
|
||||
qsfp_0_3_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_0_3_sink_logic = qsfp_0_3_sink.create_logic(qsfp_0_tx_clk_3, qsfp_0_tx_rst_3, rxd=qsfp_0_txd_3, rxc=qsfp_0_txc_3, name='qsfp_0_3_sink')
|
||||
|
||||
qsfp_1_0_source = xgmii_ep.XGMIISource()
|
||||
qsfp_1_0_source_logic = qsfp_1_0_source.create_logic(qsfp_1_rx_clk_0, qsfp_1_rx_rst_0, txd=qsfp_1_rxd_0, txc=qsfp_1_rxc_0, name='qsfp_1_0_source')
|
||||
|
||||
qsfp_1_0_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_1_0_sink_logic = qsfp_1_0_sink.create_logic(qsfp_1_tx_clk_0, qsfp_1_tx_rst_0, rxd=qsfp_1_txd_0, rxc=qsfp_1_txc_0, name='qsfp_1_0_sink')
|
||||
|
||||
qsfp_1_1_source = xgmii_ep.XGMIISource()
|
||||
qsfp_1_1_source_logic = qsfp_1_1_source.create_logic(qsfp_1_rx_clk_1, qsfp_1_rx_rst_1, txd=qsfp_1_rxd_1, txc=qsfp_1_rxc_1, name='qsfp_1_1_source')
|
||||
|
||||
qsfp_1_1_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_1_1_sink_logic = qsfp_1_1_sink.create_logic(qsfp_1_tx_clk_1, qsfp_1_tx_rst_1, rxd=qsfp_1_txd_1, rxc=qsfp_1_txc_1, name='qsfp_1_1_sink')
|
||||
|
||||
qsfp_1_2_source = xgmii_ep.XGMIISource()
|
||||
qsfp_1_2_source_logic = qsfp_1_2_source.create_logic(qsfp_1_rx_clk_2, qsfp_1_rx_rst_2, txd=qsfp_1_rxd_2, txc=qsfp_1_rxc_2, name='qsfp_1_2_source')
|
||||
|
||||
qsfp_1_2_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_1_2_sink_logic = qsfp_1_2_sink.create_logic(qsfp_1_tx_clk_2, qsfp_1_tx_rst_2, rxd=qsfp_1_txd_2, rxc=qsfp_1_txc_2, name='qsfp_1_2_sink')
|
||||
|
||||
qsfp_1_3_source = xgmii_ep.XGMIISource()
|
||||
qsfp_1_3_source_logic = qsfp_1_3_source.create_logic(qsfp_1_rx_clk_3, qsfp_1_rx_rst_3, txd=qsfp_1_rxd_3, txc=qsfp_1_rxc_3, name='qsfp_1_3_source')
|
||||
|
||||
qsfp_1_3_sink = xgmii_ep.XGMIISink()
|
||||
qsfp_1_3_sink_logic = qsfp_1_3_sink.create_logic(qsfp_1_tx_clk_3, qsfp_1_tx_rst_3, rxd=qsfp_1_txd_3, rxc=qsfp_1_txc_3, name='qsfp_1_3_sink')
|
||||
|
||||
# DUT
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
|
||||
dut = Cosimulation(
|
||||
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
user_led_g=user_led_g,
|
||||
user_led_r=user_led_r,
|
||||
front_led=front_led,
|
||||
user_sw=user_sw,
|
||||
|
||||
qsfp_0_tx_clk_0=qsfp_0_tx_clk_0,
|
||||
qsfp_0_tx_rst_0=qsfp_0_tx_rst_0,
|
||||
qsfp_0_txd_0=qsfp_0_txd_0,
|
||||
qsfp_0_txc_0=qsfp_0_txc_0,
|
||||
qsfp_0_rx_clk_0=qsfp_0_rx_clk_0,
|
||||
qsfp_0_rx_rst_0=qsfp_0_rx_rst_0,
|
||||
qsfp_0_rxd_0=qsfp_0_rxd_0,
|
||||
qsfp_0_rxc_0=qsfp_0_rxc_0,
|
||||
qsfp_0_tx_clk_1=qsfp_0_tx_clk_1,
|
||||
qsfp_0_tx_rst_1=qsfp_0_tx_rst_1,
|
||||
qsfp_0_txd_1=qsfp_0_txd_1,
|
||||
qsfp_0_txc_1=qsfp_0_txc_1,
|
||||
qsfp_0_rx_clk_1=qsfp_0_rx_clk_1,
|
||||
qsfp_0_rx_rst_1=qsfp_0_rx_rst_1,
|
||||
qsfp_0_rxd_1=qsfp_0_rxd_1,
|
||||
qsfp_0_rxc_1=qsfp_0_rxc_1,
|
||||
qsfp_0_tx_clk_2=qsfp_0_tx_clk_2,
|
||||
qsfp_0_tx_rst_2=qsfp_0_tx_rst_2,
|
||||
qsfp_0_txd_2=qsfp_0_txd_2,
|
||||
qsfp_0_txc_2=qsfp_0_txc_2,
|
||||
qsfp_0_rx_clk_2=qsfp_0_rx_clk_2,
|
||||
qsfp_0_rx_rst_2=qsfp_0_rx_rst_2,
|
||||
qsfp_0_rxd_2=qsfp_0_rxd_2,
|
||||
qsfp_0_rxc_2=qsfp_0_rxc_2,
|
||||
qsfp_0_tx_clk_3=qsfp_0_tx_clk_3,
|
||||
qsfp_0_tx_rst_3=qsfp_0_tx_rst_3,
|
||||
qsfp_0_txd_3=qsfp_0_txd_3,
|
||||
qsfp_0_txc_3=qsfp_0_txc_3,
|
||||
qsfp_0_rx_clk_3=qsfp_0_rx_clk_3,
|
||||
qsfp_0_rx_rst_3=qsfp_0_rx_rst_3,
|
||||
qsfp_0_rxd_3=qsfp_0_rxd_3,
|
||||
qsfp_0_rxc_3=qsfp_0_rxc_3,
|
||||
qsfp_1_tx_clk_0=qsfp_1_tx_clk_0,
|
||||
qsfp_1_tx_rst_0=qsfp_1_tx_rst_0,
|
||||
qsfp_1_txd_0=qsfp_1_txd_0,
|
||||
qsfp_1_txc_0=qsfp_1_txc_0,
|
||||
qsfp_1_rx_clk_0=qsfp_1_rx_clk_0,
|
||||
qsfp_1_rx_rst_0=qsfp_1_rx_rst_0,
|
||||
qsfp_1_rxd_0=qsfp_1_rxd_0,
|
||||
qsfp_1_rxc_0=qsfp_1_rxc_0,
|
||||
qsfp_1_tx_clk_1=qsfp_1_tx_clk_1,
|
||||
qsfp_1_tx_rst_1=qsfp_1_tx_rst_1,
|
||||
qsfp_1_txd_1=qsfp_1_txd_1,
|
||||
qsfp_1_txc_1=qsfp_1_txc_1,
|
||||
qsfp_1_rx_clk_1=qsfp_1_rx_clk_1,
|
||||
qsfp_1_rx_rst_1=qsfp_1_rx_rst_1,
|
||||
qsfp_1_rxd_1=qsfp_1_rxd_1,
|
||||
qsfp_1_rxc_1=qsfp_1_rxc_1,
|
||||
qsfp_1_tx_clk_2=qsfp_1_tx_clk_2,
|
||||
qsfp_1_tx_rst_2=qsfp_1_tx_rst_2,
|
||||
qsfp_1_txd_2=qsfp_1_txd_2,
|
||||
qsfp_1_txc_2=qsfp_1_txc_2,
|
||||
qsfp_1_rx_clk_2=qsfp_1_rx_clk_2,
|
||||
qsfp_1_rx_rst_2=qsfp_1_rx_rst_2,
|
||||
qsfp_1_rxd_2=qsfp_1_rxd_2,
|
||||
qsfp_1_rxc_2=qsfp_1_rxc_2,
|
||||
qsfp_1_tx_clk_3=qsfp_1_tx_clk_3,
|
||||
qsfp_1_tx_rst_3=qsfp_1_tx_rst_3,
|
||||
qsfp_1_txd_3=qsfp_1_txd_3,
|
||||
qsfp_1_txc_3=qsfp_1_txc_3,
|
||||
qsfp_1_rx_clk_3=qsfp_1_rx_clk_3,
|
||||
qsfp_1_rx_rst_3=qsfp_1_rx_rst_3,
|
||||
qsfp_1_rxd_3=qsfp_1_rxd_3,
|
||||
qsfp_1_rxc_3=qsfp_1_rxc_3
|
||||
)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
qsfp_0_tx_clk_0.next = not qsfp_0_tx_clk_0
|
||||
qsfp_0_rx_clk_0.next = not qsfp_0_rx_clk_0
|
||||
qsfp_0_tx_clk_1.next = not qsfp_0_tx_clk_1
|
||||
qsfp_0_rx_clk_1.next = not qsfp_0_rx_clk_1
|
||||
qsfp_0_tx_clk_2.next = not qsfp_0_tx_clk_2
|
||||
qsfp_0_rx_clk_2.next = not qsfp_0_rx_clk_2
|
||||
qsfp_0_tx_clk_3.next = not qsfp_0_tx_clk_3
|
||||
qsfp_0_rx_clk_3.next = not qsfp_0_rx_clk_3
|
||||
qsfp_1_tx_clk_0.next = not qsfp_1_tx_clk_0
|
||||
qsfp_1_rx_clk_0.next = not qsfp_1_rx_clk_0
|
||||
qsfp_1_tx_clk_1.next = not qsfp_1_tx_clk_1
|
||||
qsfp_1_rx_clk_1.next = not qsfp_1_rx_clk_1
|
||||
qsfp_1_tx_clk_2.next = not qsfp_1_tx_clk_2
|
||||
qsfp_1_rx_clk_2.next = not qsfp_1_rx_clk_2
|
||||
qsfp_1_tx_clk_3.next = not qsfp_1_tx_clk_3
|
||||
qsfp_1_rx_clk_3.next = not qsfp_1_rx_clk_3
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
qsfp_0_tx_rst_1.next = 1
|
||||
qsfp_0_rx_rst_1.next = 1
|
||||
qsfp_0_tx_rst_2.next = 1
|
||||
qsfp_0_rx_rst_2.next = 1
|
||||
qsfp_0_tx_rst_3.next = 1
|
||||
qsfp_0_rx_rst_3.next = 1
|
||||
qsfp_0_tx_rst_0.next = 1
|
||||
qsfp_0_rx_rst_0.next = 1
|
||||
qsfp_1_tx_rst_1.next = 1
|
||||
qsfp_1_rx_rst_1.next = 1
|
||||
qsfp_1_tx_rst_2.next = 1
|
||||
qsfp_1_rx_rst_2.next = 1
|
||||
qsfp_1_tx_rst_3.next = 1
|
||||
qsfp_1_rx_rst_3.next = 1
|
||||
qsfp_1_tx_rst_0.next = 1
|
||||
qsfp_1_rx_rst_0.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
qsfp_0_tx_rst_1.next = 0
|
||||
qsfp_0_rx_rst_1.next = 0
|
||||
qsfp_0_tx_rst_2.next = 0
|
||||
qsfp_0_rx_rst_2.next = 0
|
||||
qsfp_0_tx_rst_3.next = 0
|
||||
qsfp_0_rx_rst_3.next = 0
|
||||
qsfp_0_tx_rst_0.next = 0
|
||||
qsfp_0_rx_rst_0.next = 0
|
||||
qsfp_1_tx_rst_1.next = 0
|
||||
qsfp_1_rx_rst_1.next = 0
|
||||
qsfp_1_tx_rst_2.next = 0
|
||||
qsfp_1_rx_rst_2.next = 0
|
||||
qsfp_1_tx_rst_3.next = 0
|
||||
qsfp_1_rx_rst_3.next = 0
|
||||
qsfp_1_tx_rst_0.next = 0
|
||||
qsfp_1_rx_rst_0.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: test UDP RX packet")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame = udp_ep.UDPFrame()
|
||||
test_frame.eth_dest_mac = 0x020000000000
|
||||
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
|
||||
test_frame.eth_type = 0x0800
|
||||
test_frame.ip_version = 4
|
||||
test_frame.ip_ihl = 5
|
||||
test_frame.ip_dscp = 0
|
||||
test_frame.ip_ecn = 0
|
||||
test_frame.ip_length = None
|
||||
test_frame.ip_identification = 0
|
||||
test_frame.ip_flags = 2
|
||||
test_frame.ip_fragment_offset = 0
|
||||
test_frame.ip_ttl = 64
|
||||
test_frame.ip_protocol = 0x11
|
||||
test_frame.ip_header_checksum = None
|
||||
test_frame.ip_source_ip = 0xc0a80181
|
||||
test_frame.ip_dest_ip = 0xc0a80180
|
||||
test_frame.udp_source_port = 5678
|
||||
test_frame.udp_dest_port = 1234
|
||||
test_frame.payload = bytearray(range(32))
|
||||
test_frame.build()
|
||||
|
||||
qsfp_0_0_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data)
|
||||
|
||||
# wait for ARP request packet
|
||||
while qsfp_0_0_sink.empty():
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = qsfp_0_0_sink.recv()
|
||||
check_eth_frame = eth_ep.EthFrame()
|
||||
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
|
||||
check_frame = arp_ep.ARPFrame()
|
||||
check_frame.parse_eth(check_eth_frame)
|
||||
|
||||
print(check_frame)
|
||||
|
||||
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
|
||||
assert check_frame.eth_src_mac == 0x020000000000
|
||||
assert check_frame.eth_type == 0x0806
|
||||
assert check_frame.arp_htype == 0x0001
|
||||
assert check_frame.arp_ptype == 0x0800
|
||||
assert check_frame.arp_hlen == 6
|
||||
assert check_frame.arp_plen == 4
|
||||
assert check_frame.arp_oper == 1
|
||||
assert check_frame.arp_sha == 0x020000000000
|
||||
assert check_frame.arp_spa == 0xc0a80180
|
||||
assert check_frame.arp_tha == 0x000000000000
|
||||
assert check_frame.arp_tpa == 0xc0a80181
|
||||
|
||||
# generate response
|
||||
arp_frame = arp_ep.ARPFrame()
|
||||
arp_frame.eth_dest_mac = 0x020000000000
|
||||
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
|
||||
arp_frame.eth_type = 0x0806
|
||||
arp_frame.arp_htype = 0x0001
|
||||
arp_frame.arp_ptype = 0x0800
|
||||
arp_frame.arp_hlen = 6
|
||||
arp_frame.arp_plen = 4
|
||||
arp_frame.arp_oper = 2
|
||||
arp_frame.arp_sha = 0xDAD1D2D3D4D5
|
||||
arp_frame.arp_spa = 0xc0a80181
|
||||
arp_frame.arp_tha = 0x020000000000
|
||||
arp_frame.arp_tpa = 0xc0a80180
|
||||
|
||||
qsfp_0_0_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+arp_frame.build_eth().build_axis_fcs().data)
|
||||
|
||||
while qsfp_0_0_sink.empty():
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = qsfp_0_0_sink.recv()
|
||||
check_eth_frame = eth_ep.EthFrame()
|
||||
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
|
||||
check_frame = udp_ep.UDPFrame()
|
||||
check_frame.parse_eth(check_eth_frame)
|
||||
|
||||
print(check_frame)
|
||||
|
||||
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
|
||||
assert check_frame.eth_src_mac == 0x020000000000
|
||||
assert check_frame.eth_type == 0x0800
|
||||
assert check_frame.ip_version == 4
|
||||
assert check_frame.ip_ihl == 5
|
||||
assert check_frame.ip_dscp == 0
|
||||
assert check_frame.ip_ecn == 0
|
||||
assert check_frame.ip_identification == 0
|
||||
assert check_frame.ip_flags == 2
|
||||
assert check_frame.ip_fragment_offset == 0
|
||||
assert check_frame.ip_ttl == 64
|
||||
assert check_frame.ip_protocol == 0x11
|
||||
assert check_frame.ip_source_ip == 0xc0a80180
|
||||
assert check_frame.ip_dest_ip == 0xc0a80181
|
||||
assert check_frame.udp_source_port == 1234
|
||||
assert check_frame.udp_dest_port == 5678
|
||||
assert check_frame.payload.data == bytearray(range(32))
|
||||
|
||||
assert qsfp_0_0_source.empty()
|
||||
assert qsfp_0_0_sink.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return instances()
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
269
example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v
Normal file
269
example/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v
Normal file
@ -0,0 +1,269 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for fpga_core
|
||||
*/
|
||||
module test_fpga_core;
|
||||
|
||||
// Parameters
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [1:0] user_sw = 0;
|
||||
reg qsfp_0_tx_clk_0 = 0;
|
||||
reg qsfp_0_tx_rst_0 = 0;
|
||||
reg qsfp_0_rx_clk_0 = 0;
|
||||
reg qsfp_0_rx_rst_0 = 0;
|
||||
reg [63:0] qsfp_0_rxd_0 = 0;
|
||||
reg [7:0] qsfp_0_rxc_0 = 0;
|
||||
reg qsfp_0_tx_clk_1 = 0;
|
||||
reg qsfp_0_tx_rst_1 = 0;
|
||||
reg qsfp_0_rx_clk_1 = 0;
|
||||
reg qsfp_0_rx_rst_1 = 0;
|
||||
reg [63:0] qsfp_0_rxd_1 = 0;
|
||||
reg [7:0] qsfp_0_rxc_1 = 0;
|
||||
reg qsfp_0_tx_clk_2 = 0;
|
||||
reg qsfp_0_tx_rst_2 = 0;
|
||||
reg qsfp_0_rx_clk_2 = 0;
|
||||
reg qsfp_0_rx_rst_2 = 0;
|
||||
reg [63:0] qsfp_0_rxd_2 = 0;
|
||||
reg [7:0] qsfp_0_rxc_2 = 0;
|
||||
reg qsfp_0_tx_clk_3 = 0;
|
||||
reg qsfp_0_tx_rst_3 = 0;
|
||||
reg qsfp_0_rx_clk_3 = 0;
|
||||
reg qsfp_0_rx_rst_3 = 0;
|
||||
reg [63:0] qsfp_0_rxd_3 = 0;
|
||||
reg [7:0] qsfp_0_rxc_3 = 0;
|
||||
reg qsfp_1_tx_clk_0 = 0;
|
||||
reg qsfp_1_tx_rst_0 = 0;
|
||||
reg qsfp_1_rx_clk_0 = 0;
|
||||
reg qsfp_1_rx_rst_0 = 0;
|
||||
reg [63:0] qsfp_1_rxd_0 = 0;
|
||||
reg [7:0] qsfp_1_rxc_0 = 0;
|
||||
reg qsfp_1_tx_clk_1 = 0;
|
||||
reg qsfp_1_tx_rst_1 = 0;
|
||||
reg qsfp_1_rx_clk_1 = 0;
|
||||
reg qsfp_1_rx_rst_1 = 0;
|
||||
reg [63:0] qsfp_1_rxd_1 = 0;
|
||||
reg [7:0] qsfp_1_rxc_1 = 0;
|
||||
reg qsfp_1_tx_clk_2 = 0;
|
||||
reg qsfp_1_tx_rst_2 = 0;
|
||||
reg qsfp_1_rx_clk_2 = 0;
|
||||
reg qsfp_1_rx_rst_2 = 0;
|
||||
reg [63:0] qsfp_1_rxd_2 = 0;
|
||||
reg [7:0] qsfp_1_rxc_2 = 0;
|
||||
reg qsfp_1_tx_clk_3 = 0;
|
||||
reg qsfp_1_tx_rst_3 = 0;
|
||||
reg qsfp_1_rx_clk_3 = 0;
|
||||
reg qsfp_1_rx_rst_3 = 0;
|
||||
reg [63:0] qsfp_1_rxd_3 = 0;
|
||||
reg [7:0] qsfp_1_rxc_3 = 0;
|
||||
|
||||
// Outputs
|
||||
wire [1:0] user_led_g;
|
||||
wire user_led_r;
|
||||
wire [1:0] front_led;
|
||||
wire [63:0] qsfp_0_txd_0;
|
||||
wire [7:0] qsfp_0_txc_0;
|
||||
wire [63:0] qsfp_0_txd_1;
|
||||
wire [7:0] qsfp_0_txc_1;
|
||||
wire [63:0] qsfp_0_txd_2;
|
||||
wire [7:0] qsfp_0_txc_2;
|
||||
wire [63:0] qsfp_0_txd_3;
|
||||
wire [7:0] qsfp_0_txc_3;
|
||||
wire [63:0] qsfp_1_txd_0;
|
||||
wire [7:0] qsfp_1_txc_0;
|
||||
wire [63:0] qsfp_1_txd_1;
|
||||
wire [7:0] qsfp_1_txc_1;
|
||||
wire [63:0] qsfp_1_txd_2;
|
||||
wire [7:0] qsfp_1_txc_2;
|
||||
wire [63:0] qsfp_1_txd_3;
|
||||
wire [7:0] qsfp_1_txc_3;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk,
|
||||
rst,
|
||||
current_test,
|
||||
user_sw,
|
||||
qsfp_0_tx_clk_0,
|
||||
qsfp_0_tx_rst_0,
|
||||
qsfp_0_rx_clk_0,
|
||||
qsfp_0_rx_rst_0,
|
||||
qsfp_0_rxd_0,
|
||||
qsfp_0_rxc_0,
|
||||
qsfp_0_tx_clk_1,
|
||||
qsfp_0_tx_rst_1,
|
||||
qsfp_0_rx_clk_1,
|
||||
qsfp_0_rx_rst_1,
|
||||
qsfp_0_rxd_1,
|
||||
qsfp_0_rxc_1,
|
||||
qsfp_0_tx_clk_2,
|
||||
qsfp_0_tx_rst_2,
|
||||
qsfp_0_rx_clk_2,
|
||||
qsfp_0_rx_rst_2,
|
||||
qsfp_0_rxd_2,
|
||||
qsfp_0_rxc_2,
|
||||
qsfp_0_tx_clk_3,
|
||||
qsfp_0_tx_rst_3,
|
||||
qsfp_0_rx_clk_3,
|
||||
qsfp_0_rx_rst_3,
|
||||
qsfp_0_rxd_3,
|
||||
qsfp_0_rxc_3,
|
||||
qsfp_1_tx_clk_0,
|
||||
qsfp_1_tx_rst_0,
|
||||
qsfp_1_rx_clk_0,
|
||||
qsfp_1_rx_rst_0,
|
||||
qsfp_1_rxd_0,
|
||||
qsfp_1_rxc_0,
|
||||
qsfp_1_tx_clk_1,
|
||||
qsfp_1_tx_rst_1,
|
||||
qsfp_1_rx_clk_1,
|
||||
qsfp_1_rx_rst_1,
|
||||
qsfp_1_rxd_1,
|
||||
qsfp_1_rxc_1,
|
||||
qsfp_1_tx_clk_2,
|
||||
qsfp_1_tx_rst_2,
|
||||
qsfp_1_rx_clk_2,
|
||||
qsfp_1_rx_rst_2,
|
||||
qsfp_1_rxd_2,
|
||||
qsfp_1_rxc_2,
|
||||
qsfp_1_tx_clk_3,
|
||||
qsfp_1_tx_rst_3,
|
||||
qsfp_1_rx_clk_3,
|
||||
qsfp_1_rx_rst_3,
|
||||
qsfp_1_rxd_3,
|
||||
qsfp_1_rxc_3
|
||||
);
|
||||
$to_myhdl(
|
||||
user_led_g,
|
||||
user_led_r,
|
||||
front_led,
|
||||
qsfp_0_txd_0,
|
||||
qsfp_0_txc_0,
|
||||
qsfp_0_txd_1,
|
||||
qsfp_0_txc_1,
|
||||
qsfp_0_txd_2,
|
||||
qsfp_0_txc_2,
|
||||
qsfp_0_txd_3,
|
||||
qsfp_0_txc_3,
|
||||
qsfp_1_txd_0,
|
||||
qsfp_1_txc_0,
|
||||
qsfp_1_txd_1,
|
||||
qsfp_1_txc_1,
|
||||
qsfp_1_txd_2,
|
||||
qsfp_1_txc_2,
|
||||
qsfp_1_txd_3,
|
||||
qsfp_1_txc_3
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_fpga_core.lxt");
|
||||
$dumpvars(0, test_fpga_core);
|
||||
end
|
||||
|
||||
fpga_core
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.user_led_g(user_led_g),
|
||||
.user_led_r(user_led_r),
|
||||
.front_led(front_led),
|
||||
.user_sw(user_sw),
|
||||
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0),
|
||||
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0),
|
||||
.qsfp_0_txd_0(qsfp_0_txd_0),
|
||||
.qsfp_0_txc_0(qsfp_0_txc_0),
|
||||
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0),
|
||||
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0),
|
||||
.qsfp_0_rxd_0(qsfp_0_rxd_0),
|
||||
.qsfp_0_rxc_0(qsfp_0_rxc_0),
|
||||
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1),
|
||||
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1),
|
||||
.qsfp_0_txd_1(qsfp_0_txd_1),
|
||||
.qsfp_0_txc_1(qsfp_0_txc_1),
|
||||
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1),
|
||||
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1),
|
||||
.qsfp_0_rxd_1(qsfp_0_rxd_1),
|
||||
.qsfp_0_rxc_1(qsfp_0_rxc_1),
|
||||
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2),
|
||||
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2),
|
||||
.qsfp_0_txd_2(qsfp_0_txd_2),
|
||||
.qsfp_0_txc_2(qsfp_0_txc_2),
|
||||
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2),
|
||||
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2),
|
||||
.qsfp_0_rxd_2(qsfp_0_rxd_2),
|
||||
.qsfp_0_rxc_2(qsfp_0_rxc_2),
|
||||
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3),
|
||||
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3),
|
||||
.qsfp_0_txd_3(qsfp_0_txd_3),
|
||||
.qsfp_0_txc_3(qsfp_0_txc_3),
|
||||
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3),
|
||||
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3),
|
||||
.qsfp_0_rxd_3(qsfp_0_rxd_3),
|
||||
.qsfp_0_rxc_3(qsfp_0_rxc_3),
|
||||
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0),
|
||||
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0),
|
||||
.qsfp_1_txd_0(qsfp_1_txd_0),
|
||||
.qsfp_1_txc_0(qsfp_1_txc_0),
|
||||
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0),
|
||||
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0),
|
||||
.qsfp_1_rxd_0(qsfp_1_rxd_0),
|
||||
.qsfp_1_rxc_0(qsfp_1_rxc_0),
|
||||
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1),
|
||||
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1),
|
||||
.qsfp_1_txd_1(qsfp_1_txd_1),
|
||||
.qsfp_1_txc_1(qsfp_1_txc_1),
|
||||
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1),
|
||||
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1),
|
||||
.qsfp_1_rxd_1(qsfp_1_rxd_1),
|
||||
.qsfp_1_rxc_1(qsfp_1_rxc_1),
|
||||
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2),
|
||||
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2),
|
||||
.qsfp_1_txd_2(qsfp_1_txd_2),
|
||||
.qsfp_1_txc_2(qsfp_1_txc_2),
|
||||
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2),
|
||||
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2),
|
||||
.qsfp_1_rxd_2(qsfp_1_rxd_2),
|
||||
.qsfp_1_rxc_2(qsfp_1_rxc_2),
|
||||
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3),
|
||||
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3),
|
||||
.qsfp_1_txd_3(qsfp_1_txd_3),
|
||||
.qsfp_1_txc_3(qsfp_1_txc_3),
|
||||
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3),
|
||||
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3),
|
||||
.qsfp_1_rxd_3(qsfp_1_rxd_3),
|
||||
.qsfp_1_rxc_3(qsfp_1_rxc_3)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1
example/ADM_PCIE_9V3/fpga_25g/tb/udp_ep.py
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/tb/udp_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/udp_ep.py
|
||||
1
example/ADM_PCIE_9V3/fpga_25g/tb/xgmii_ep.py
Symbolic link
1
example/ADM_PCIE_9V3/fpga_25g/tb/xgmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/xgmii_ep.py
|
||||
Loading…
x
Reference in New Issue
Block a user