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https://github.com/alexforencich/verilog-ethernet.git
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Unconditionally wait at least one delta cycle
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ced2df141c
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@ -409,6 +409,7 @@ class AXIStreamSink(object):
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return not self.active
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def wait(self, timeout=0):
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yield delay(0)
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if self.queue:
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return
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if timeout:
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@ -114,6 +114,7 @@ class LocalLinkSink(object):
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return not self.queue
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def wait(self, timeout=0):
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yield delay(0)
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if self.queue:
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return
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if timeout:
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