merged changes in axis

lib/axis/rtl/arbiter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Arbiter module
@@ -153,3 +155,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream bus width adapter
@@ -552,3 +554,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_arb_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream arbitrated multiplexer
@@ -250,3 +252,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_arb_mux_wrap.py

@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port arbitrated mux (wrapper)
@@ -163,6 +165,8 @@ axis_arb_mux_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_async_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream asynchronous FIFO
@@ -618,3 +620,5 @@ always @(posedge m_clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_async_fifo_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream asynchronous FIFO with width converter
@@ -353,3 +355,5 @@ fifo_inst (
 );
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_broadcast.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream broadcaster
@@ -189,3 +191,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_broadcast_wrap.py

@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port broadcast (wrapper)
@@ -158,6 +160,8 @@ axis_broadcast_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_cobs_decode.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream consistent overhead byte stuffing (COBS) decoder
@@ -326,3 +328,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_cobs_encode.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream consistent overhead byte stuffing (COBS) encoder
@@ -504,3 +506,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_crosspoint.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream crosspoint
@@ -149,3 +151,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_crosspoint_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{m}}x{{n}} crosspoint (wrapper)
@@ -170,6 +172,8 @@ axis_crosspoint_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_demux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream demultiplexer
@@ -264,3 +266,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_demux_wrap.py

@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port demux (wrapper)
@@ -166,6 +168,8 @@ axis_demux_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream FIFO
@@ -301,3 +303,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_fifo_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream FIFO with width converter
@@ -343,3 +345,5 @@ fifo_inst (
 );
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_frame_join.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame joiner
@@ -325,3 +327,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_frame_join_wrap.py

@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port frame joiner (wrapper)
@@ -138,6 +140,8 @@ axis_frame_join_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_frame_len.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame length measurement
@@ -108,3 +110,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_frame_length_adjust.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame length adjuster
@@ -611,3 +613,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_frame_length_adjust_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame length adjuster with FIFO
@@ -235,3 +237,5 @@ header_fifo_inst (
 );
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_ll_bridge.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream to LocalLink bridge
@@ -77,3 +79,5 @@ assign ll_eof_out_n = !(s_axis_tlast && !invalid);
 assign ll_src_rdy_out_n = !(s_axis_tvalid && !invalid);
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream multiplexer
@@ -261,3 +263,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_mux_wrap.py

@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port mux (wrapper)
@@ -163,6 +165,8 @@ axis_mux_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_pipeline_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream pipeline FIFO
@@ -254,3 +256,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_pipeline_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream pipeline register
@@ -156,3 +158,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_ram_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream RAM switch
@@ -1102,3 +1104,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_ram_switch_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{m}}x{{n}} RAM switch (wrapper)
@@ -237,6 +239,8 @@ axis_ram_switch_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_rate_limit.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream rate limiter
@@ -254,3 +256,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -274,3 +276,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_srl_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream SRL-based FIFO
@@ -193,3 +195,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_srl_register.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream SRL-based FIFO register
@@ -152,3 +154,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_stat_counter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream statistics counter
@@ -364,3 +366,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream switch
@@ -371,3 +373,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall

lib/axis/rtl/axis_switch_wrap.py

@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{m}}x{{n}} switch (wrapper)
@@ -197,6 +199,8 @@ axis_switch_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

lib/axis/rtl/axis_tap.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream tap
@@ -326,3 +328,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

lib/axis/rtl/ll_axis_bridge.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * LocalLink to AXI4-Stream bridge
@@ -62,3 +64,5 @@ assign m_axis_tlast = !ll_eof_in_n;
 assign ll_dst_rdy_out_n = !m_axis_tready;
 
 endmodule
+
+`resetall

lib/axis/rtl/priority_encoder.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Priority encoder module
@@ -86,3 +88,5 @@ assign output_encoded = stage_enc[LEVELS-1];
 assign output_unencoded = 1 << output_encoded;
 
 endmodule
+
+`resetall

lib/axis/rtl/sync_reset.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -55,3 +57,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall