diff --git a/lib/axis/rtl/arbiter.v b/lib/axis/rtl/arbiter.v
index cd55dd3d..cfac70d1 100644
--- a/lib/axis/rtl/arbiter.v
+++ b/lib/axis/rtl/arbiter.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Arbiter module
@@ -153,3 +155,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_adapter.v b/lib/axis/rtl/axis_adapter.v
index 68b31a50..cb332510 100644
--- a/lib/axis/rtl/axis_adapter.v
+++ b/lib/axis/rtl/axis_adapter.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream bus width adapter
@@ -552,3 +554,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_arb_mux.v b/lib/axis/rtl/axis_arb_mux.v
index 092ae1f2..5f8eb2dd 100644
--- a/lib/axis/rtl/axis_arb_mux.v
+++ b/lib/axis/rtl/axis_arb_mux.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream arbitrated multiplexer
@@ -250,3 +252,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_arb_mux_wrap.py b/lib/axis/rtl/axis_arb_mux_wrap.py
index 7abab28a..4cfe2b8f 100755
--- a/lib/axis/rtl/axis_arb_mux_wrap.py
+++ b/lib/axis/rtl/axis_arb_mux_wrap.py
@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port arbitrated mux (wrapper)
@@ -163,6 +165,8 @@ axis_arb_mux_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_async_fifo.v b/lib/axis/rtl/axis_async_fifo.v
index e37573c3..c190b7b0 100644
--- a/lib/axis/rtl/axis_async_fifo.v
+++ b/lib/axis/rtl/axis_async_fifo.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream asynchronous FIFO
@@ -618,3 +620,5 @@ always @(posedge m_clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_async_fifo_adapter.v b/lib/axis/rtl/axis_async_fifo_adapter.v
index 5fbce1bc..76a293a6 100644
--- a/lib/axis/rtl/axis_async_fifo_adapter.v
+++ b/lib/axis/rtl/axis_async_fifo_adapter.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream asynchronous FIFO with width converter
@@ -353,3 +355,5 @@ fifo_inst (
 );
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_broadcast.v b/lib/axis/rtl/axis_broadcast.v
index d2f305fc..16137ea7 100644
--- a/lib/axis/rtl/axis_broadcast.v
+++ b/lib/axis/rtl/axis_broadcast.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream broadcaster
@@ -189,3 +191,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_broadcast_wrap.py b/lib/axis/rtl/axis_broadcast_wrap.py
index 43a46c1f..e755a20e 100755
--- a/lib/axis/rtl/axis_broadcast_wrap.py
+++ b/lib/axis/rtl/axis_broadcast_wrap.py
@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port broadcast (wrapper)
@@ -158,6 +160,8 @@ axis_broadcast_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_cobs_decode.v b/lib/axis/rtl/axis_cobs_decode.v
index aed0b1ef..84f50470 100644
--- a/lib/axis/rtl/axis_cobs_decode.v
+++ b/lib/axis/rtl/axis_cobs_decode.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream consistent overhead byte stuffing (COBS) decoder
@@ -326,3 +328,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_cobs_encode.v b/lib/axis/rtl/axis_cobs_encode.v
index e62b98ef..c88e95cb 100644
--- a/lib/axis/rtl/axis_cobs_encode.v
+++ b/lib/axis/rtl/axis_cobs_encode.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream consistent overhead byte stuffing (COBS) encoder
@@ -504,3 +506,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_crosspoint.v b/lib/axis/rtl/axis_crosspoint.v
index 8fcf6a89..c6574d26 100644
--- a/lib/axis/rtl/axis_crosspoint.v
+++ b/lib/axis/rtl/axis_crosspoint.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream crosspoint
@@ -149,3 +151,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_crosspoint_wrap.py b/lib/axis/rtl/axis_crosspoint_wrap.py
index defcb46f..f7396532 100755
--- a/lib/axis/rtl/axis_crosspoint_wrap.py
+++ b/lib/axis/rtl/axis_crosspoint_wrap.py
@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{m}}x{{n}} crosspoint (wrapper)
@@ -170,6 +172,8 @@ axis_crosspoint_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_demux.v b/lib/axis/rtl/axis_demux.v
index 011db4b8..50b63359 100644
--- a/lib/axis/rtl/axis_demux.v
+++ b/lib/axis/rtl/axis_demux.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream demultiplexer
@@ -264,3 +266,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_demux_wrap.py b/lib/axis/rtl/axis_demux_wrap.py
index 4bd36d5f..8f69561d 100755
--- a/lib/axis/rtl/axis_demux_wrap.py
+++ b/lib/axis/rtl/axis_demux_wrap.py
@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port demux (wrapper)
@@ -166,6 +168,8 @@ axis_demux_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_fifo.v b/lib/axis/rtl/axis_fifo.v
index 0fee4708..5e27849e 100644
--- a/lib/axis/rtl/axis_fifo.v
+++ b/lib/axis/rtl/axis_fifo.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream FIFO
@@ -301,3 +303,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_fifo_adapter.v b/lib/axis/rtl/axis_fifo_adapter.v
index d9fa325c..7b43b007 100644
--- a/lib/axis/rtl/axis_fifo_adapter.v
+++ b/lib/axis/rtl/axis_fifo_adapter.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream FIFO with width converter
@@ -343,3 +345,5 @@ fifo_inst (
 );
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_frame_join.v b/lib/axis/rtl/axis_frame_join.v
index 018d8cc6..d25f5c6e 100644
--- a/lib/axis/rtl/axis_frame_join.v
+++ b/lib/axis/rtl/axis_frame_join.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame joiner
@@ -325,3 +327,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_frame_join_wrap.py b/lib/axis/rtl/axis_frame_join_wrap.py
index 0a05fd48..e7c66908 100755
--- a/lib/axis/rtl/axis_frame_join_wrap.py
+++ b/lib/axis/rtl/axis_frame_join_wrap.py
@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port frame joiner (wrapper)
@@ -138,6 +140,8 @@ axis_frame_join_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_frame_len.v b/lib/axis/rtl/axis_frame_len.v
index 4c944b64..a1f75e5d 100644
--- a/lib/axis/rtl/axis_frame_len.v
+++ b/lib/axis/rtl/axis_frame_len.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame length measurement
@@ -108,3 +110,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_frame_length_adjust.v b/lib/axis/rtl/axis_frame_length_adjust.v
index 55257cb1..42550ad0 100644
--- a/lib/axis/rtl/axis_frame_length_adjust.v
+++ b/lib/axis/rtl/axis_frame_length_adjust.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame length adjuster
@@ -611,3 +613,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_frame_length_adjust_fifo.v b/lib/axis/rtl/axis_frame_length_adjust_fifo.v
index ce0acd74..a580cee9 100644
--- a/lib/axis/rtl/axis_frame_length_adjust_fifo.v
+++ b/lib/axis/rtl/axis_frame_length_adjust_fifo.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream frame length adjuster with FIFO
@@ -235,3 +237,5 @@ header_fifo_inst (
 );
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_ll_bridge.v b/lib/axis/rtl/axis_ll_bridge.v
index ad0e0021..af956dde 100644
--- a/lib/axis/rtl/axis_ll_bridge.v
+++ b/lib/axis/rtl/axis_ll_bridge.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream to LocalLink bridge
@@ -77,3 +79,5 @@ assign ll_eof_out_n = !(s_axis_tlast && !invalid);
 assign ll_src_rdy_out_n = !(s_axis_tvalid && !invalid);
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_mux.v b/lib/axis/rtl/axis_mux.v
index 716f9af5..ba97d939 100644
--- a/lib/axis/rtl/axis_mux.v
+++ b/lib/axis/rtl/axis_mux.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream multiplexer
@@ -261,3 +263,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_mux_wrap.py b/lib/axis/rtl/axis_mux_wrap.py
index 3e9370b9..bc1b8325 100755
--- a/lib/axis/rtl/axis_mux_wrap.py
+++ b/lib/axis/rtl/axis_mux_wrap.py
@@ -61,7 +61,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port mux (wrapper)
@@ -163,6 +165,8 @@ axis_mux_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_pipeline_fifo.v b/lib/axis/rtl/axis_pipeline_fifo.v
index c293f9bc..01c97fd9 100644
--- a/lib/axis/rtl/axis_pipeline_fifo.v
+++ b/lib/axis/rtl/axis_pipeline_fifo.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream pipeline FIFO
@@ -254,3 +256,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_pipeline_register.v b/lib/axis/rtl/axis_pipeline_register.v
index 99d8b853..1e22ffcc 100644
--- a/lib/axis/rtl/axis_pipeline_register.v
+++ b/lib/axis/rtl/axis_pipeline_register.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream pipeline register
@@ -156,3 +158,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_ram_switch.v b/lib/axis/rtl/axis_ram_switch.v
index de9ff475..c936232c 100644
--- a/lib/axis/rtl/axis_ram_switch.v
+++ b/lib/axis/rtl/axis_ram_switch.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream RAM switch
@@ -1102,3 +1104,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_ram_switch_wrap.py b/lib/axis/rtl/axis_ram_switch_wrap.py
index 56c47ab7..6e07113f 100755
--- a/lib/axis/rtl/axis_ram_switch_wrap.py
+++ b/lib/axis/rtl/axis_ram_switch_wrap.py
@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{m}}x{{n}} RAM switch (wrapper)
@@ -237,6 +239,8 @@ axis_ram_switch_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_rate_limit.v b/lib/axis/rtl/axis_rate_limit.v
index bebe1b3c..3f91b4cb 100644
--- a/lib/axis/rtl/axis_rate_limit.v
+++ b/lib/axis/rtl/axis_rate_limit.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream rate limiter
@@ -254,3 +256,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_register.v b/lib/axis/rtl/axis_register.v
index 609e9d3e..fbd245c1 100644
--- a/lib/axis/rtl/axis_register.v
+++ b/lib/axis/rtl/axis_register.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream register
@@ -274,3 +276,5 @@ end
 endgenerate
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_srl_fifo.v b/lib/axis/rtl/axis_srl_fifo.v
index 53f1d311..e0cc4164 100644
--- a/lib/axis/rtl/axis_srl_fifo.v
+++ b/lib/axis/rtl/axis_srl_fifo.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream SRL-based FIFO
@@ -193,3 +195,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_srl_register.v b/lib/axis/rtl/axis_srl_register.v
index 1548d341..4bfaeaaf 100644
--- a/lib/axis/rtl/axis_srl_register.v
+++ b/lib/axis/rtl/axis_srl_register.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream SRL-based FIFO register
@@ -152,3 +154,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_stat_counter.v b/lib/axis/rtl/axis_stat_counter.v
index b68fbdd4..c59c441b 100644
--- a/lib/axis/rtl/axis_stat_counter.v
+++ b/lib/axis/rtl/axis_stat_counter.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream statistics counter
@@ -364,3 +366,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_switch.v b/lib/axis/rtl/axis_switch.v
index 875a061d..4688d639 100644
--- a/lib/axis/rtl/axis_switch.v
+++ b/lib/axis/rtl/axis_switch.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream switch
@@ -371,3 +373,5 @@ generate
 endgenerate
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/axis_switch_wrap.py b/lib/axis/rtl/axis_switch_wrap.py
index 8e1078d0..d7d3bbfc 100755
--- a/lib/axis/rtl/axis_switch_wrap.py
+++ b/lib/axis/rtl/axis_switch_wrap.py
@@ -67,7 +67,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{m}}x{{n}} switch (wrapper)
@@ -197,6 +199,8 @@ axis_switch_inst (
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")
diff --git a/lib/axis/rtl/axis_tap.v b/lib/axis/rtl/axis_tap.v
index 543010e4..a9c7e19e 100644
--- a/lib/axis/rtl/axis_tap.v
+++ b/lib/axis/rtl/axis_tap.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream tap
@@ -326,3 +328,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/ll_axis_bridge.v b/lib/axis/rtl/ll_axis_bridge.v
index ab2aeab0..3628dcb5 100644
--- a/lib/axis/rtl/ll_axis_bridge.v
+++ b/lib/axis/rtl/ll_axis_bridge.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * LocalLink to AXI4-Stream bridge
@@ -62,3 +64,5 @@ assign m_axis_tlast = !ll_eof_in_n;
 assign ll_dst_rdy_out_n = !m_axis_tready;
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/priority_encoder.v b/lib/axis/rtl/priority_encoder.v
index dd59fa45..cf82512b 100644
--- a/lib/axis/rtl/priority_encoder.v
+++ b/lib/axis/rtl/priority_encoder.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Priority encoder module
@@ -86,3 +88,5 @@ assign output_encoded = stage_enc[LEVELS-1];
 assign output_unencoded = 1 << output_encoded;
 
 endmodule
+
+`resetall
diff --git a/lib/axis/rtl/sync_reset.v b/lib/axis/rtl/sync_reset.v
index 65c5cfa7..8c2dd529 100644
--- a/lib/axis/rtl/sync_reset.v
+++ b/lib/axis/rtl/sync_reset.v
@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Synchronizes an active-high asynchronous reset signal to a given clock by
@@ -55,3 +57,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall