From 1f793fa7d02543e63681fbcb2647cafd5843daa6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 8 Jan 2019 17:24:22 -0800 Subject: [PATCH] Update readme --- example/ExaNIC_X10/fpga/README.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/example/ExaNIC_X10/fpga/README.md b/example/ExaNIC_X10/fpga/README.md index f2d77ef1..c11efb3d 100644 --- a/example/ExaNIC_X10/fpga/README.md +++ b/example/ExaNIC_X10/fpga/README.md @@ -6,8 +6,7 @@ This example design targets the Exablaze ExaNIC X10 FPGA board. The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly -to ARP requests. The design also enables the gigabit Ethernet interface for -testing with a QSFP loopback adapter. +to ARP requests. FPGA: xcku035-fbva676-2-c PHY: 10G BASE-R PHY IP core and internal GTH transceiver