From 218d3f1b0f6a406eed0d6a6abf574545c95f36cb Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 26 Feb 2015 19:05:56 -0800 Subject: [PATCH] Add assert for error_bad_fcs signal --- tb/test_axis_eth_fcs_check.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tb/test_axis_eth_fcs_check.py b/tb/test_axis_eth_fcs_check.py index a51919e5..89d623f5 100755 --- a/tb/test_axis_eth_fcs_check.py +++ b/tb/test_axis_eth_fcs_check.py @@ -160,6 +160,13 @@ def bench(): def clkgen(): clk.next = not clk + error_bad_fcs_asserted = Signal(bool(0)) + + @always(clk.posedge) + def monitor(): + if (error_bad_fcs): + error_bad_fcs_asserted.next = 1 + def wait_normal(): while input_axis_tvalid or output_axis_tvalid: yield clk.posedge @@ -371,6 +378,8 @@ def bench(): axis_frame1.data[-1] ^= 0xff for wait in wait_normal, wait_pause_source, wait_pause_sink: + error_bad_fcs_asserted.next = 0 + source_queue.put(axis_frame1) source_queue.put(axis_frame2) yield clk.posedge @@ -382,6 +391,8 @@ def bench(): yield clk.posedge yield clk.posedge + assert error_bad_fcs_asserted + rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() @@ -405,7 +416,7 @@ def bench(): raise StopSimulation - return dut, source, sink, clkgen, check + return dut, monitor, source, sink, clkgen, check def test_bench(): sim = Simulation(bench())