FPGA/verilog-ethernet
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Update example design

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This commit is contained in:
Alex Forencich 2020-12-25 01:47:01 -08:00
parent 2a2d8ac966
commit 220e04d1a7
3 changed files with 7 additions and 6 deletions
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3
example/HXT100G/fpga_cxpt16/fpga/Makefile
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@ -21,8 +21,7 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_crosspoint.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v

7
example/HXT100G/fpga_cxpt16/rtl/fpga_core.v
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@ -309,8 +309,11 @@ eth_mac_fifo_inst (
.ifg_delay(12)
);
eth_axis_rx_64
eth_axis_rx_inst (
eth_axis_rx #(
.DATA_WIDTH(64),
.KEEP_WIDTH(8)
)
eth_axis_rxinst (
.clk(clk),
.rst(rst),
// AXI input

3
example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py
View File

@ -40,8 +40,7 @@ srcs.append("../lib/eth/rtl/eth_mac_10g.v")
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_crosspoint.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v")