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merged changes in axis

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Alex Forencich 2024-02-05 17:30:40 -08:00
commit 22abe6cacb
1 changed files with 9 additions and 1 deletions
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10
lib/axis/rtl/axis_ram_switch.v
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@ -611,7 +611,9 @@ generate
assign int_cmd_len[m*ADDR_WIDTH +: ADDR_WIDTH] = cmd_len_reg;
assign int_cmd_id[m*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH] = cmd_id_reg;
assign int_cmd_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH] = cmd_tkeep_reg;
assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT] = cmd_tid_reg;
if (ID_ENABLE && S_ID_WIDTH > 0) begin
assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT] = cmd_tid_reg;
end
assign int_cmd_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] = cmd_tdest_reg;
assign int_cmd_tuser[m*USER_WIDTH +: USER_WIDTH] = cmd_tuser_reg;
assign int_cmd_valid[m*M_COUNT +: M_COUNT] = cmd_valid_reg;
@ -910,11 +912,17 @@ generate
assign port_cmd_status_ready[m] = int_cmd_status_ready[m*M_COUNT+n];
end
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DATA_WIDTH-1:0] out_fifo_tdata[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg out_fifo_tlast[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [M_ID_WIDTH-1:0] out_fifo_tid[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [M_DEST_WIDTH-1:0] out_fifo_tdest[31:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [USER_WIDTH-1:0] out_fifo_tuser[31:0];
reg [5:0] out_fifo_data_wr_ptr_reg = 0;