Detect bad XGMII encodings in PHY TX

rtl/eth_phy_10g.v

@@ -69,6 +69,7 @@ module eth_phy_10g #
     /*
      * Status
      */
+    output wire                  tx_bad_block,
     output wire [6:0]            rx_error_count,
     output wire                  rx_bad_block,
     output wire                  rx_sequence_error,
@@ -126,6 +127,7 @@ eth_phy_10g_tx_inst (
     .xgmii_txc(xgmii_txc),
     .serdes_tx_data(serdes_tx_data),
     .serdes_tx_hdr(serdes_tx_hdr),
+    .tx_bad_block(tx_bad_block),
     .tx_prbs31_enable(tx_prbs31_enable)
 );
 

rtl/eth_phy_10g_tx.v

@@ -55,6 +55,11 @@ module eth_phy_10g_tx #
     output wire [DATA_WIDTH-1:0] serdes_tx_data,
     output wire [HDR_WIDTH-1:0]  serdes_tx_hdr,
 
+    /*
+     * Status
+     */
+    output wire                  tx_bad_block,
+
     /*
      * Configuration
      */
@@ -93,7 +98,8 @@ xgmii_baser_enc_inst (
     .xgmii_txd(xgmii_txd),
     .xgmii_txc(xgmii_txc),
     .encoded_tx_data(encoded_tx_data),
-    .encoded_tx_hdr(encoded_tx_hdr)
+    .encoded_tx_hdr(encoded_tx_hdr),
+    .tx_bad_block(tx_bad_block)
 );
 
 eth_phy_10g_tx_if #(

rtl/xgmii_baser_enc_64.v

@@ -49,7 +49,12 @@ module xgmii_baser_enc_64 #
      * 10GBASE-R encoded interface
      */
     output wire [DATA_WIDTH-1:0] encoded_tx_data,
-    output wire [HDR_WIDTH-1:0]  encoded_tx_hdr
+    output wire [HDR_WIDTH-1:0]  encoded_tx_hdr,
+
+    /*
+     * Status
+     */
+    output wire                  tx_bad_block
 );
 
 // bus width assertions
@@ -127,13 +132,17 @@ reg [CTRL_WIDTH-1:0] encode_err;
 reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {DATA_WIDTH{1'b0}}, encoded_tx_data_next;
 reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = {HDR_WIDTH{1'b0}}, encoded_tx_hdr_next;
 
+reg tx_bad_block_reg = 1'b0, tx_bad_block_next;
+
 assign encoded_tx_data = encoded_tx_data_reg;
 assign encoded_tx_hdr = encoded_tx_hdr_reg;
 
+assign tx_bad_block = tx_bad_block_reg;
+
 integer i;
 
 always @* begin
-
+    tx_bad_block_next = 1'b0;
 
     for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
         if (xgmii_txc[i]) begin
@@ -190,55 +199,72 @@ always @* begin
     if (xgmii_txc == 8'h00) begin
         encoded_tx_data_next = xgmii_txd;
         encoded_tx_hdr_next = SYNC_DATA;
+        tx_bad_block_next = 1'b0;
     end else begin
         if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_SEQ_OS) begin
             // ordered set in lane 4
             encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, encoded_ctrl[27:0], BLOCK_TYPE_OS_4};
+            tx_bad_block_next = encode_err[3:0] != 0;
         end else if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_START) begin
             // start in lane 4
             encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, encoded_ctrl[27:0], BLOCK_TYPE_START_4};
+            tx_bad_block_next = encode_err[3:0] != 0;
         end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_START) begin
             // ordered set in lane 0, start in lane 4
             encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_START};
+            tx_bad_block_next = 1'b0;
         end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_SEQ_OS) begin
             // ordered set in lane 0 and lane 4
             encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_04};
+            tx_bad_block_next = 1'b0;
         end else if (xgmii_txc == 8'h01 && xgmii_txd[7:0] == XGMII_START) begin
             // start in lane 0
             encoded_tx_data_next = {xgmii_txd[63:8], BLOCK_TYPE_START_0};
+            tx_bad_block_next = 1'b0;
         end else if (xgmii_txc == 8'hf1 && xgmii_txd[7:0] == XGMII_SEQ_OS) begin
             // ordered set in lane 0
             encoded_tx_data_next = {encoded_ctrl[55:28], O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_0};
+            tx_bad_block_next = encode_err[7:4] != 0;
         end else if (xgmii_txc == 8'hff && xgmii_txd[7:0] == XGMII_TERM) begin
             // terminate in lane 0
             encoded_tx_data_next = {encoded_ctrl[55:7], 7'd0, BLOCK_TYPE_TERM_0};
+            tx_bad_block_next = encode_err[7:1] != 0;
         end else if (xgmii_txc == 8'hfe && xgmii_txd[15:8] == XGMII_TERM) begin
             // terminate in lane 1
             encoded_tx_data_next = {encoded_ctrl[55:14], 6'd0, xgmii_txd[7:0], BLOCK_TYPE_TERM_1};
+            tx_bad_block_next = encode_err[7:2] != 0;
         end else if (xgmii_txc == 8'hfc && xgmii_txd[23:16] == XGMII_TERM) begin
             // terminate in lane 2
             encoded_tx_data_next = {encoded_ctrl[55:21], 5'd0, xgmii_txd[15:0], BLOCK_TYPE_TERM_2};
+            tx_bad_block_next = encode_err[7:3] != 0;
         end else if (xgmii_txc == 8'hf8 && xgmii_txd[31:24] == XGMII_TERM) begin
             // terminate in lane 3
             encoded_tx_data_next = {encoded_ctrl[55:28], 4'd0, xgmii_txd[23:0], BLOCK_TYPE_TERM_3};
+            tx_bad_block_next = encode_err[7:4] != 0;
         end else if (xgmii_txc == 8'hf0 && xgmii_txd[39:32] == XGMII_TERM) begin
             // terminate in lane 4
             encoded_tx_data_next = {encoded_ctrl[55:35], 3'd0, xgmii_txd[31:0], BLOCK_TYPE_TERM_4};
+            tx_bad_block_next = encode_err[7:5] != 0;
         end else if (xgmii_txc == 8'he0 && xgmii_txd[47:40] == XGMII_TERM) begin
             // terminate in lane 5
             encoded_tx_data_next = {encoded_ctrl[55:42], 2'd0, xgmii_txd[39:0], BLOCK_TYPE_TERM_5};
+            tx_bad_block_next = encode_err[7:6] != 0;
         end else if (xgmii_txc == 8'hc0 && xgmii_txd[55:48] == XGMII_TERM) begin
             // terminate in lane 6
             encoded_tx_data_next = {encoded_ctrl[55:49], 1'd0, xgmii_txd[47:0], BLOCK_TYPE_TERM_6};
+            tx_bad_block_next = encode_err[7] != 0;
         end else if (xgmii_txc == 8'h80 && xgmii_txd[63:56] == XGMII_TERM) begin
             // terminate in lane 7
             encoded_tx_data_next = {xgmii_txd[55:0], BLOCK_TYPE_TERM_7};
+            tx_bad_block_next = 1'b0;
         end else if (xgmii_txc == 8'hff) begin
             // all control
             encoded_tx_data_next = {encoded_ctrl, BLOCK_TYPE_CTRL};
+            tx_bad_block_next = encode_err != 0;
         end else begin
             // no corresponding block format
             encoded_tx_data_next = {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
+            tx_bad_block_next = 1'b1;
         end
         encoded_tx_hdr_next = SYNC_CTRL;
     end
@@ -247,6 +273,8 @@ end
 always @(posedge clk) begin
     encoded_tx_data_reg <= encoded_tx_data_next;
     encoded_tx_hdr_reg <= encoded_tx_hdr_next;
+
+    tx_bad_block_reg <= tx_bad_block_next;
 end
 
 endmodule