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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Insert idle characters
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parent
b195c6450b
commit
25e196e18b
@ -189,23 +189,26 @@ class XGMIISource(object):
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dl.append(0xfd)
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cl.append(1)
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k = 0
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d = 0
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c = 0
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if bw == 8 and ifg_cnt >= 4:
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ifg_cnt = max(ifg_cnt-4, 0)
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k = 4
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d = 0x07070707
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c = 0xf
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dl = [0x07]*4+dl
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cl = [1]*4+cl
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deficit_idle_cnt = ifg_cnt
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ifg_cnt = 0
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for i in range(k,bw):
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d = 0
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c = 0
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for i in range(0,bw):
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if dl:
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d |= dl.pop(0) << (8*i)
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c |= cl.pop(0) << i
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if not dl:
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ifg_cnt = max(ifg, 12) - (bw-i) + deficit_idle_cnt
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else:
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d |= 0x07 << (8*i)
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c |= 1 << i
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txd.next = d
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txc.next = c
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